The disclosure provides a semiconductor structure, a layout of the semiconductor structure and a semiconductor device. The semiconductor structure includes: a plurality of first conductive layers which are spaced; a plurality of capacitor banks, and the capacitor bank being on the first conductive layer in one-to-one correspondence and the capacitor bank including at least a capacitor, each of the capacitor including a lower electrode layer, a capacitance dielectric layer and an upper electrode layer stacked from bottom to top; a capacitor plate, which is on each of the upper electrode layer; and a second conductive layer, which is above the capacitor plate and connected with the capacitor plate.

Methods and semiconductor devices are described herein which eliminate the use of additional masks. A first interconnect layer is formed. A first resistive layer is formed on top of the first interconnect layer. A dielectric layer is formed on top of the first resistive layer. A second resistive layer is formed on top of the dielectric layer.

Methods and semiconductor devices are described herein which eliminate the use of additional masks. A first interconnect layer is formed. A first resistive layer is formed on top of the first interconnect layer. A dielectric layer is formed on top of the first resistive layer. A second resistive layer is formed on top of the dielectric layer.

A moat trench laterally surrounding a device region is formed in a substrate. A conductive metallic substrate enclosure structure is formed in the moat trench. Deep trenches are formed in the substrate, and a trench capacitor structure is formed in the deep trenches. The substrate may be thinned by removing a backside portion of the substrate. A backside surface of the conductive metallic substrate enclosure structure is physically exposed. A backside metal layer is formed on a backside surface of the substrate and a backside surface of the conductive metallic substrate enclosure structure. A metallic interconnect enclosure structure and a metallic cap plate may be formed to provide a metallic shield structure configured to block electromagnetic radiation from impinging into the trench capacitor structure.

RC-network components that include a substrate and capacitor having a thin-film top electrode portion at a surface on one side of the substrate. The low ohmic semiconductor substrate is doped to contribute 5% or less to the resistance of the RC-network component. The resistance provided in series with the capacitor is controlled by providing a contact plate, spaced from the thin-film top electrode portion by an insulating layer, and a set of one or more bridging contacts passing through openings in the insulating layer. The bridging contacts electrically interconnect the thin-film top electrode portion and the contact plate. Different resistance values can be set by appropriate selection of the number of bridging contacts. The openings are elongated thereby reducing temperature concentration at their periphery. Correspondingly, the bridging contacts have an elongated cross-sectional shape.

An electronic circuit comprises a first resistor (1) and a second resistor (2). The first resistor comprises: a first sheet (10) of resistive material; and a first pair (11, 12) of conductive contacts, each arranged in electrical contact with the first sheet, and arranged such that a shortest resistive path in the first sheet between the first pair of contacts passes through the first sheet and has a length equal to a thickness (LI) of the first sheet. The second resistor comprises: a second sheet (20) of resistive material; and a second pair (21, 22) of conductive contacts, each arranged in electrical contact with the second sheet, and arranged such that a shortest resistive path (L2) in the second sheet between the second pair of contacts passes along at least a portion of a length of the second sheet.

An electronic circuit comprises a first resistor (1) and a second resistor (2). The first resistor comprises: a first sheet (10) of resistive material; and a first pair (11, 12) of conductive contacts, each arranged in electrical contact with the first sheet, and arranged such that a shortest resistive path in the first sheet between the first pair of contacts passes through the first sheet and has a length equal to a thickness (LI) of the first sheet. The second resistor comprises: a second sheet (20) of resistive material; and a second pair (21, 22) of conductive contacts, each arranged in electrical contact with the second sheet, and arranged such that a shortest resistive path (L2) in the second sheet between the second pair of contacts passes along at least a portion of a length of the second sheet.

A semiconductor structure includes an interposer substrate having an upper surface, a lower surface opposite to the upper surface, and a device region. A first redistribution layer is formed on the upper surface of the interposer substrate. A guard ring is formed in the interposer substrate and surrounds the device region. At least a through-silicon via (TSV) is formed in the interposer substrate. An end of the guard ring and an end of the TSV that are near the upper surface of the interposer substrate are flush with each other, and are electrically connected to the first redistribution layer.

A semiconductor structure includes an interposer substrate having an upper surface, a lower surface opposite to the upper surface, and a device region. A first redistribution layer is formed on the upper surface of the interposer substrate. A guard ring is formed in the interposer substrate and surrounds the device region. At least a through-silicon via (TSV) is formed in the interposer substrate. An end of the guard ring and an end of the TSV that are near the upper surface of the interposer substrate are flush with each other, and are electrically connected to the first redistribution layer.

An electronic device is provided that includes a board equipped with a pair of differential transmission lines that each have an opening extending between two line terminals. Moreover, the device includes a capacitor module that includes a support and two capacitors that each have two capacitor terminals, respectively, connected to the two line terminals of one line of the pair of transmission lines. In addition, the support includes a separating region between the two capacitors that has at least one cavity disposed between the two capacitors.