A semiconductor device including a transistor section and a diode section, the semiconductor device having: a temperature sensing section; a neighboring transistor section adjacent to the temperature sensing section; a neighboring diode section adjacent to the temperature sensing section; and a first non-neighboring diode section that is not adjacent to the temperature sensing section, wherein the first non-neighboring diode section has a pattern different from the pattern of the neighboring diode section in the top view is provided.

Provided is a semiconductor device with a reduced variation in temperature among a plurality of unit transistors. A semiconductor device includes: a semiconductor substrate; and a transistor group including at least one column in which a plurality of unit transistors are aligned and arranged along a first axis on the semiconductor substrate. A first column of the at least one column includes: a first group of transistors including two of the unit transistors that are adjacent to each other with a first distance therebetween, and a second group of transistors including two of the unit transistors that are adjacent to each other with a second distance therebetween, the first group of transistors is disposed at a position closer to a center of the first column along the first axis than the second group of transistors, and the first distance is larger than the second distance.

Power amplifier having staggered cascode layout for enhanced thermal ruggedness. In some embodiments, a radio-frequency (RF) amplifier such as a power amplifier (PA) can be configured to receive and amplify an RF signal. The PA can include an array of cascoded devices connected electrically parallel between an input node and an output node. Each cascoded device can include a common emitter transistor and a common base transistor arranged in a cascode configuration. The array can be configured such that the common base transistors are positioned in a staggered orientation relative to each other.

A semiconductor device for simultaneous operation at two temperature ranges includes a substrate, a first transistor, and a second transistor. The substrate has a first active region and a second active region. The first transistor includes a plurality of gate stacks disposed in the first active region. The second transistor includes a plurality of gate stacks disposed in the second active region. A ratio of the number of the gate stacks of the second transistor to an area size of the second active region is less than a ratio of the number of the gate stacks of the first transistor to an area size of the first active region.

An electrostatic discharge (ESD) protection device includes a substrate including a device region and an ESD protection structure formed on the substrate in the device region. The device region includes a center region and edge regions separated by the center region, while the ESD protection structure includes a plurality of gate structures. The ESD protection device also includes a dielectric layer formed to cover the plurality of gate structures and a plurality of heat dissipation structures formed on the dielectric layer with each heat dissipation structure aligned with a corresponding gate structure along a direction perpendicular to a surface of the substrate. The area size of each heat dissipation structure aligned with a corresponding gate structure in the center region is larger than the area size of each heat dissipation structure aligned with a corresponding gate structure in the edge region.

A bandgap voltage reference circuit includes first and second transistors (e.g., 3-terminal BJTs or diode-connected BJTs), and a PTAT element (e.g., resistance or capacitance). The first transistor is at a first die location, and operates with a first base-emitter voltage. The second transistor is at a second die location, and operates with a second base-emitter voltage. Each of the first and second transistors may include multiple individual parallel-connected transistors. The PTAT element is operatively coupled to the first and second transistors such that a voltage difference between the first and second base-emitter voltages drops across the PTAT element. The first and second locations are separated by a distance (e.g., 1.5% or more of die length, or such that the respective centroids of the first and second transistor are spaced from one another). Such spatial distribution helps mitigate voltage shift induced by mechanical stress, and is insensitive to process variation.

According to various aspects, a thermal-aware finned field-effect transistor (FinFET) may have a design that can substantially reduce hot spot temperatures and resolve other self-heating problems. More particularly, the FinFET design may use aluminum nitride (AlN) fins that can provide a main thermal exit and a source, drain, and channel formed from materials that can spread or dissipate heat, wherein AlN has a high thermal conductivity compared to silicon such that using AlN to form the fins may substantially increase heat flux to a silicon substrate relative to silicon fins. Furthermore, thermal-efficient materials may be used to form the source, drain, and channel structures to further spread heat and decrease hot spot temperatures.

An integrated circuit is provided. The integrated circuit includes a continuous resistor body having first and second distal terminals, and a group of electrically-floating dummy conductors that are formed above the continuous resistor body, and between the first and second distal terminals of the continuous resistor body. Each of the group of dummy conductors is coupled to the continuous resistor body through a respective via structure. The group of dummy conductors serves to dissipate heat for the continuous resistor body. If desired, an active conductor is interposed in the dummy conductors and serves as a center-tap for the continuous resistor body. The active conductor is connected to a contact node on the substrate.

A semiconductor device includes transistor cells in a semiconductor portion, wherein the transistor cells are electrically connected to a gate metallization, a source electrode and a drain electrode. In one example, the semiconductor device further includes a doped region in the semiconductor portion. The doped region is electrically connected to the source electrode. A resistance of the doped region has a negative temperature coefficient. An interlayer dielectric separates the gate metallization from the doped region. A drain structure in the semiconductor portion electrically connects the transistor cells with the drain electrode and forms a pn junction with the doped region.

A semiconductor die includes a structural body that has a power region and a peripheral region surrounding the power region. At least one power device is positioned in the power region. Trench-insulation means extend in the structural body starting from the front side towards the back side along a first direction, adapted to hinder conduction of heat from the power region towards the peripheral region along a second direction orthogonal to the first direction. The trench-insulation means have an extension, in the second direction, greater than the thickness of the structural body along the first direction.