Integrated semiconductor devices and method of making the integrated semiconductor are disclosed. The integrated semiconductor device may include a first transistor comprising a first gate and at least one first active region, a second transistor comprising a second gate and at least one second active region, wherein the second transistor is spaced a first distance from the first transistor, a dielectric sidewall spacer formed on a gate sidewall of the first transistor and a gate sidewall of the second transistor, a first dielectric layer formed over the first transistor and the second transistor, wherein a thickness of the first dielectric layer is greater than half the first distance, and a patterned metal layer formed on the first dielectric layer and partially covering the second gate.

The present disclosure relates to a semi-conductor structure and method for co-integrating a III-V device with a group IV device on a Si.sub.xGe.sub.1-x(100) substrate. The method includes: (a) providing a Si.sub.xGe.sub.1-x(100) substrate, where x is from 0 to 1; (b) selecting a first region for forming therein a group IV device and a second region for forming therein a III-V device, the first and the second region each comprising a section of the Si.sub.xGe.sub.1-x(100) substrate; (c) forming a trench isolation for at least the III-V device; (d) providing a Si.sub.yGe.sub.1-y(100) surface in the first region, where y is from 0 to 1; (e) at least partially forming the group IV device on the Si.sub.yGe.sub.1-y(100) surface in the first region; (f) forming a trench in the second region which exposes the Si.sub.xGe.sub.1-x(100) substrate, the trench having a depth of at least 200 nm, at least 500 nm, at least 1 μm, usually at least 2 μm, such as 4 μm, with respect to the Si.sub.yGe.sub.1-y(100) surface in the first region; (g) growing a III-V material in the trench using aspect ratio trapping; and (h) forming the III-V device on the III-V material, the III-V device comprising at least one contact region at a height within 100 nm, 50 nm, 20 nm, usually 10 nm, of a contact region of the group IV device.

A 3D semiconductor device including: a first level including a single crystal silicon layer and a plurality of first transistors, the plurality of first transistors each including a single crystal channel; a first metal layer overlaying the plurality of first transistors; a second metal layer overlaying the first metal layer; a third metal layer overlaying the second metal layer; a second level is disposed above the third metal layer, where the second level includes a plurality of second transistors; a fourth metal layer disposed above the second level; and a connective path between the fourth metal layer and either the third metal layer or the second metal layer, where the connective path includes a via disposed through the second level, where the via has a diameter of less than 800 nm and greater than 5 nm, and where at least one of the plurality of second transistors includes a metal gate.

Various embodiments of the present application are directed towards a method to integrate NVM devices with a logic or BCD device. In some embodiments, an isolation structure is formed in a semiconductor substrate. The isolation structure demarcates a memory region of the semiconductor substrate, and further demarcates a peripheral region of the semiconductor substrate. The peripheral region may, for example, correspond to BCD device or a logic device. A doped well is formed in the peripheral region. A dielectric seal layer is formed covering the memory and peripheral regions, and further covering the doped well. The dielectric seal layer is removed from the memory region, but not the peripheral region. A memory cell structure is formed on the memory region using a thermal oxidation process. The dielectric seal layer is removed from the peripheral region, and a peripheral device structure including a gate electrode is formed on the peripheral region.

Embodiments of the disclosure provide a bipolar transistor structure including a semiconductor fin on a substrate. The semiconductor fin has a first doping type, a length in a first direction, and a width in a second direction perpendicular to the first direction. A first emitter/collector (E/C) material is adjacent a first sidewall of the semiconductor fin along the width of the semiconductor fin. The first E/C material has a second doping type opposite the first doping type. A second E/C material is adjacent a second sidewall of the semiconductor fin along the width of the semiconductor fin. The second E/C material has the second doping type. A width of the first E/C material is different from a width of the second E/C material.

A semiconductor device and fabrication method are described for manufacturing a heterojunction bipolar transistor by forming a silicon collector region in a substrate which includes a lower collector layer, a dopant diffusion barrier layer, and an upper collector layer, where the formation of the dopant diffusion barrier layer reduces diffusion of dopants from the lower collector layer into the upper collector layer during one or more subsequent manufacturing steps which are used to form a trench isolation region in the substrate along with a heterogeneous base region and a silicon emitter region.

A semiconductor device or circuit includes a vertical bipolar junction transistor (vBJT) and a vertical filed effect transistor (vFET). The vBJT collector is electrically and/or physically connected to an adjacent vFET source. For example, a vBJT collector and a vFET source may be integrated upon a same semiconductor material substrate or layer. The vFET provides negative feedback for the collector-base voltage and the vBJT emitter and collector allow for low transit times.

A 3D semiconductor device including: a first level including a plurality of first metal layers; a second level, where the second level overlays the first level, where the second level includes at least one single crystal silicon layer, where the second level includes a plurality of transistors, where each transistor of the plurality of transistors includes a single crystal channel, where the second level includes a plurality of second metal layers, where the plurality of second metal layers include interconnections between the transistors of the plurality of transistors, and where the second level is overlaid by a first isolation layer; and a connective path between the plurality of transistors and the plurality of first metal layers, where the connective path includes a via disposed through at least the single crystal silicon layer, and where the via includes contact with at least one of the plurality of transistors.

A 3D semiconductor device including: a first level including a single crystal silicon layer and a plurality of first transistors, the plurality of first transistors each including a single crystal channel; a first metal layer overlaying the plurality of first transistors; a second metal layer overlaying the first metal layer; a third metal layer overlaying the second metal layer; a second level is disposed above the third metal layer, where the second level includes a plurality of second transistors; a fourth metal layer disposed above the second level; and a connective path between the fourth metal layer and either the third metal layer or the second metal layer, where the connective path includes a via disposed through the second level, where the via has a diameter of less than 800 nm and greater than 5 nm, and where at least one of the plurality of second transistors includes a metal gate.

An integrated circuit includes a bipolar transistor, e.g. a back-ballasted NPN, that can conduct laterally and vertically. At a low voltage breakdown and low current conduction occur laterally near a substrate surface, while at a higher voltage vertical conduction occurs in a more highly-doped channel below the surface. A relatively high-resistance region at the surface has a low doping level to guide the conduction deeper into the collector.