We disclose a III-nitride semiconductor based heterojunction power device comprising: a first heterojunction transistor formed on a substrate, the first heterojunction transistor comprising: a first III-nitride semiconductor region formed over the substrate, wherein the first III-nitride semiconductor region comprises a first heterojunction comprising at least one two dimensional carrier gas; a first terminal operatively connected to the first III-nitride semiconductor region; a second terminal laterally spaced from the first terminal and operatively connected to the first III-nitride semiconductor region; a first plurality of highly doped semiconductor regions of a first polarity formed over the first III-nitride semiconductor region, the first plurality of highly doped semiconductor regions being formed between the first terminal and the second terminal; a first gate region operatively connected to the first plurality of highly doped semiconductor regions; and a second heterojunction transistor formed on the substrate. The second heterojunction transistor comprises: a second III-nitride semiconductor region formed over the substrate, wherein the second III-nitride semiconductor region comprises a second heterojunction comprising at least one two dimensional carrier gas; a third terminal operatively connected to the second III-nitride semiconductor region; a fourth terminal laterally spaced from the third terminal in the first dimension and operatively connected to the second III-nitride semiconductor region; a second gate region being formed over the second III-nitride semiconductor region, and between the third terminal and the fourth terminal. One of the first and second heterojunction transistors is an enhancement mode field effect transistor and the other of the first and second heterojunction transistors is a depletion mode field effect transistor.

The present disclosure generally relates to a semiconductor device having a capacitor and a resistor and a method of forming the same. More particularly, the present disclosure relates to a metal-insulator-metal (MIM) capacitor and a thin film resistor (TFR) formed in a back end of line portion of an integrated circuit (IC) chip.

A semiconductor device structure and a manufacturing method thereof are provided. The semiconductor device structure includes a semiconductor substrate having an active component region and a non-active component region, a first dielectric layer, a second dielectric layer, high resistivity metal segments, dummy stacked structures and a metal connection structure. The high resistivity metal segments are formed in the second dielectric layer and located in the non-active component region. The dummy stacked structures are located in the non-active component region, and at least one dummy stacked structure penetrates through the first dielectric layer and the second dielectric layer and is located between two adjacent high resistivity metal segments. The metal connection structure is disposed on the second dielectric layer, and the high resistivity metal segments are electrically connected to one another through the metal connection structure.

The object is to provide a semiconductor device that prevents a snapback operation and has excellent heat dissipation. The semiconductor device includes a semiconductor substrate, transistor portions, diode portions, a surface electrode, and external wiring. The transistor portions and the diode portions are provided in the semiconductor substrate and are arranged in one direction parallel with the surface of the semiconductor substrate. A bonding portion of the external wiring is connected to the surface electrode. The transistor portions and the diode portions are provided in a first region and a second region and alternately arranged in the one direction. A first transistor width and a first diode width in the first region are smaller than a width of the bonding portion. A second transistor width and a second diode width in the second region are larger than the width of the bonding portion.

Methods and semiconductor circuits are described in which a polysilicon resistor body is formed over a semiconductor substrate. A first dopant species is implanted into the polysilicon resistor body at a first angle about parallel to a surface normal of a topmost surface of the polysilicon resistor body. A second dopant species is implanted into the polysilicon resistor body at a second angle greater than about 10° relative to the surface normal. The combination of implants reduces the different between the temperature coefficient (tempco) of resistance of narrow resistors relative to the tempco of wide resistors, and brings the tempco of the resistors closer to a preferred value of zero.

A semiconductor device includes a junction field effect transistor (JFET) including a source electrode, a drain electrode, and a gate electrode, and a metal oxide semiconductor field effect transistor (MOSFET) including a source electrode, a drain electrode, and a gate electrode. The JFET and the MOSFET are cascode-connected such that the source electrode of the JFET and the drain electrode of the MOSFET are electrically connected. A gate voltage dependency of the JFET or a capacitance ratio of a mirror capacitance of the MOSFET to an input capacitance of the MOSFET is adjusted in a predetermined range.

A semiconductor device includes a MOSFET including a drift layer, a channel layer, a trench gate structure, a source layer, a drain layer, a source electrode, and a drain electrode. The trench gate structure includes a trench penetrating the channel layer and protruding into the drift layer, a gate insulating film disposed on a wall surface of the trench, and a gate electrode disposed on the gate insulating film. A portion of the trench protruding into the drift layer is entirely covered with a well layer, and the well layer is connected to the channel layer.

In a semiconductor device, a semiconductor substrate has an IGBT region and a FWD, and includes a first conductivity type drift layer, a second conductivity type base layer disposed on the drift layer, a second conductivity type collector layer disposed opposite to the base layer with respect to the drift layer in the IGBT region, and a first conductivity type cathode layer disposed opposite to the base layer with respect to the drift layer in the FWD region. The collector layer includes an extension portion that covers only a part of the cathode layer on a side adjacent to the drift layer. Alternatively, the collector layer includes an extension portion that entirely covers a region of the cathode layer adjacent to the drift layer, and has an area density of 3.5×10.sup.12 cm.sup.−2 or less.

An apparatus includes a first drain/source region and a second drain/source region surrounded by an isolation ring formed over a substrate, the isolation ring formed being configured to be floating, and a first diode connected between the substrate and the isolation ring, wherein the first diode is a Schottky diode.

Disclosed is an amplifying circuit and method. In one embodiment, an amplifying circuit, includes: a common-gate (CG) amplifier, wherein the CG amplifier comprises a first transistor, wherein source terminal and body terminal of the first transistor is coupled together through a first resistor.