A biased-transistor-module comprising: a module-input-terminal; a module-output-terminal; a reference-terminal; a module-supply-terminal configured to receive a supply voltage; a module-reference-voltage-terminal configured to receive a module reference voltage; a main-transistor having a main-control-terminal, a main-first-conduction-channel-terminal and a main-second-conduction-channel-terminal, wherein the main-first-conduction-channel-terminal is connected to the module-output-terminal, and the main-second-conduction-channel-terminal is connected to the reference-terminal, and the main-control-terminal is connected to an input-signal-node, wherein the input-signal-node is connected to the module-input-terminal; and a bias-circuit. The bias-circuit comprises: a first-bias-transistor; a first-bias-resistor; a second-bias-transistor; and a second-bias-resistor.

A semiconductor device comprises a vertical power device, such as a superjunction MOSFET, an IGBT, a diode, and the like, and a surface device that comprises one or more lateral devices that are electrically active along a top surface of the semiconductor device.

A semiconductor device in which a transistor and a diode are formed on a common semiconductor substrate is provided. The semiconductor substrate includes a transistor region in which a transistor is formed and a diode region in which a diode is formed. At least one first electrode on a second main surface side of the transistor region and at least one second electrode on a second main surface side of the diode region are made of different materials.

A vertical power semiconductor device is described. The vertical power semiconductor device includes a semiconductor body having a first main surface and a second main surface opposite to the first main surface. A thickness of the semiconductor body between the first main surface and the second main surface ranges from 40 μm to 200 μm. Active device elements are formed in the semiconductor body at the first main surface. Edge termination elements at least partly surround the active device elements at the first main surface. A diffusion region extends into the semiconductor body from the second main surface. A doping concentration profile of the diffusion region decreases from a peak concentration Ns at the second main surface to a concentration Ns/e, e being Euler's number, over a vertical distance ranging from 1 μm to 5 μm.

A circuit element is formed on a substrate made of a compound semiconductor. A bonding pad is disposed on the circuit element so as to at least partially overlap the circuit element. The bonding pad includes a first metal film and a second metal film formed on the first metal film. A metal material of the second metal film has a higher Young's modulus than a metal material of the first metal film.

Semiconductor structures with electrical isolation and methods of forming a semiconductor structure with electrical isolation. A shallow trench isolation region, which contains a dielectric material, is positioned in a semiconductor substrate. A trench extendes through the shallow trench isolation region and to a trench bottom in the semiconductor substrate beneath the shallow trench isolation region. A dielectric layer at least partially fills the trench. A polycrystalline region, which is arranged in the semiconductor substrate, includes a portion that is positioned beneath the trench bottom.

A semiconductor apparatus comprises a semiconductor substrate, a dummy trench section which is formed in a front surface of the semiconductor substrate, and a first front-surface-side electrode which is formed above the front surface of the semiconductor substrate and contains metals, and the dummy trench section has a dummy trench formed in the front surface of the semiconductor substrate, an insulation film formed on an inner wall of the dummy trench, a dummy conductive section formed inside the dummy trench on an inner side than the insulation film, and a protection section having an opening to expose at least a part of the dummy conductive section and covering the insulation film on the front surface of the semiconductor substrate, and the first front-surface-side electrode has a portion formed within the opening of the protection section and contacts with the dummy conductive section.

A semiconductor apparatus that includes a semiconductor substrate having a first main surface and a second main surface, a first electrode opposing the first main surface of the semiconductor substrate, a dielectric layer between the semiconductor substrate and the first electrode, a second electrode opposing the second main surface of the semiconductor substrate, and a resistance control layer between the semiconductor substrate and the second electrode. The resistance control layer includes a first region having a first electrical resistivity and electrically connecting the semiconductor substrate and the second electrode, and a second region having a second electrical resistivity higher than the first electrical resistivity of the first region and adjacent to the first region.

A semiconductor device in which a transistor and a diode are formed on a common semiconductor substrate is provided. The semiconductor substrate includes a transistor region in which a transistor is formed and a diode region in which a diode is formed. At least one first electrode on a second main surface side of the transistor region and at least one second electrode on a second main surface side of the diode region are made of different materials.

In some embodiments, a semiconductor device is provided, including a first doped region of a first conductivity type configured as a first terminal of a first diode, a second doped region of a second conductivity type configured as a second terminal of the first diode, wherein the first and second doped regions are coupled to a first voltage terminal; a first well of the first conductivity type surrounding the first and second doped regions in a layout view; a third doped region of the first conductivity type configured as a first terminal, coupled to an input/output pad, of a second diode; and a second well of the second conductivity type surrounding the third doped region in the layout view. The second and third doped regions, the first well, and the second well are configured as a first electrostatic discharge path between the I/O pad and the first voltage terminal.