The disclosure provides an electronic device. The electronic device includes a substrate, a transistor, and a variable capacitor. The transistor is disposed on the substrate. The variable capacitor is disposed on the substrate and adjacent to the transistor. A material of the transistor and a material of the variable capacitor both a include a III-V semiconductor material. The electronic device of an embodiment of the disclosure may simplify manufacturing process, reduce costs, or reduce dimensions.

A built-in resistor electrically connecting a trench gate electrode and a gate pad is formed of a conductive film formed on a semiconductor substrate via an insulating film. Here, a film thickness of the insulating film is larger than a film thickness of an insulating film in a trench and is smaller than an insulating film which is a field oxide film.

A semiconductor having transistors arranged side by side in one direction over a surface of a substrate and are connected in parallel. At least one passive element is disposed on at least one of regions between two adjacent ones of the transistors. The transistors each include a collector layer over the substrate, a base layer on the collector layer, and an emitter layer on the base layer. Collector electrodes are arranged in such a manner that each of the collector electrodes is located between the substrate and the collector layer of the corresponding one of the transistors and is electrically connected to the collector layer.

A target element to be protected and a protrusion are arranged on a substrate. An insulating film arranged on the substrate covers the target element and at least a side surface of the protrusion. An electrode pad for external connection is arranged on the insulating film. The electrode pad at least partially overlaps the target element and the protrusion as seen in plan view. A maximum distance between the upper surface of the protrusion and the electrode pad in the height direction is shorter than a maximum distance between the upper surface of the target element and the electrode pad in the height direction.

A sensor device includes a vertically stacked cascode bipolar junction transistor pair, and a first trench having a first sidewall, wherein a portion of the first sidewall is provided by the first sensing surface, wherein a bipolar junction transistor and a dual-base bipolar junction transistor of the cascode bipolar junction transistor pair are stacked vertically along the first trench.

A plurality of unit transistors that are connected in parallel to each other are formed on a substrate. In addition, a ground bump is provided on the substrate. A plurality of first capacitors are each provided for a corresponding one of the plurality of unit transistors and each connect an output electrode of the corresponding one of the plurality of unit transistors and the ground bump to each other.

A semiconductor device includes a semiconductor substrate SUB, a semiconductor layer EP formed on the semiconductor substrate SUB, a buried layer PBL formed between the semiconductor layer EP and the semiconductor substrate SUB, an isolation layer PiSO formed in the semiconductor layer EP so as to be in contact with the buried layer PBL, and a conductive film FG formed over the isolation layer PiSO via an insulating film IF, whereby a first capacitive element including the conductive film FG as an upper electrode, the insulating film IF as a capacitive insulating film, and the isolation layer PiSO as a lower electrode, is formed over the semiconductor substrate SUB.

Between a source electrode (25) of a main device (24) and a current sensing electrode (22) of a current detection device (21), a resistor for detecting current is connected. Dielectric withstand voltage of gate insulator (36) is larger than a product of the resistor and maximal current flowing through the current detection device (21) with reverse bias. A diffusion length of a p-body region (32) of the main device (24) is shorter than that of a p-body (31) of the current detection device (21). A curvature radius at an end portion of the p-body region (32) of the main device (24) is smaller than that of the p-body (31) of the current detection device (21). As a result, at the inverse bias, electric field at the end portion of the p-body region (32) of the main device (24) becomes stronger than that of the p-body region (31) of the current detection device (21). Consequently, avalanche breakdown tends to occur earlier in the main device 24 than the current detection device (21).

A device includes a first region, a second region disposed on the first region, a third region and a fourth region abutting the third region disposed in the second region, a fifth region disposed in the third region and coupled to a collector disposed above, and a sixth region disposed in the fourth region and coupled to an emitter disposed above. A first isolation is disposed between the collector and the emitter. A seventh region is disposed in the fifth region and coupled to the collector is spaced apart from the first isolation. The first region, the third region, the fifth region, the collector and the emitter have a first conductivity type different from a second conductivity type that the second region, the fourth region, the sixth region and the seventh region have.

Solder bumps are placed in direct contact with the silicon substrate of an amplifier integrated circuit having a flip chip configuration. A plurality of amplifier transistor arrays generate waste heat that promotes thermal run away of the amplifier if not directed out of the integrated circuit. The waste heat flows through the thermally conductive silicon substrate and out the solder bump to a heat-sinking plane of an interposer connected to the amplifier integrated circuit via the solder bumps.