An integrated circuit (IC) includes a lower group III-N layer having a first composition over a substrate, and an upper group III-N layer having a different second composition over the lower group III-N layer. A gate electrode of a High Electron Mobility Transistor (HEMT) is located over the upper group III-N layer. First and second resistor contacts make a conductive connection to the lower group III-N layer. An unbiased group III-N cover layer is located on the upper group III-N layer in a resistor area including a high Rs 2-DEG resistor, where the unbiased group III-N cover layer is positioned between the first and second contacts.

A method of forming a resistor circuit, the method comprising forming a first resistor comprising a first type of resistor, forming a second resistor comprising a second type of resistor, the first type of resistor being different from the second type of resistor and simultaneously doping a first part of the first resistor and a second part of the second resistor, the first resistor and the second resistor being configured such that doping of the first part of the first resistor and the second part of the second resistor defines a temperature coefficient of the first resistor and a temperature coefficient of the second resistor, wherein the temperature coefficient of the first resistor and the temperature coefficient of the second resistor have opposite signs.

A plurality of first wiring layers are arranged on a main surface of a substrate, a first insulating film is arranged on upper faces of the plurality of first wiring layers, a second insulating film is arranged on an upper face of the first insulating film, and a plurality of second wiring layers are arranged on the second insulating film. A metal resistive element layer is arranged just below at least one second wiring layer among the plurality of second wiring layers. A plurality of conductive layers extend from the plurality of second wiring layers respectively to the metal resistive element layer in a Z direction perpendicular to the main surface. The metal resistive element layer includes a metal wiring layer. At least one part of a side face of at least one conductive layer among the plurality of conductive layers is connected to the metal wiring layer.

A semiconductor device includes: an n.sup.+-type drain region deposited at an upper part of a p-type semiconductor base body; an n-type drift region deposited to be in contact with the n.sup.+-type drain region; an n.sup.+-type source region opposed to the n.sup.+-type drain region with the n-type drift region interposed; a p-type gate region deposited to be in contact with the n-type drift region; an interlayer insulating film covering the n-type drift region; a resistive element having a spiral-like planar shape provided inside the interlayer insulating film; a drain electrode wire connected to the n.sup.+-type drain region and one end of the resistive element; a source electrode wire connected to the n.sup.+-type source region; a gate electrode wire connected to the p-type gate region; and a potential-dividing terminal wire connected to the resistive element, wherein a gap between the source electrode wire and an outermost circumference of the resistive element is constant.

High voltage semiconductor devices are described herein. An exemplary semiconductor device includes a first doped region and a second doped region disposed in a substrate. The first doped region and the second doped region are oppositely doped and adjacently disposed in the substrate. A first isolation structure and a second isolation structure are disposed over the substrate, such that each are disposed at least partially over the first doped region. The first isolation structure is spaced apart from the second isolation structure. A resistor is disposed over a portion of the first isolation structure and electrically coupled to the first doped region. A field plate disposed over a portion of the second doped region and electrically coupled to the second doped region.

Disclosed is a semiconductor device that suppresses stress-induced resistance value changes. The semiconductor device includes a resistance correction circuit. The resistance correction circuit includes a first resistor whose stress-resistance value relationship is a first relationship, a second resistor whose stress-resistance value relationship is a second relationship, and a correction section that controls the resistance value of a correction target resistor. The correction section detects the difference between the resistance value of the first resistor and the resistance value of the second resistor and corrects, in accordance with the result of detection, the resistance value of the correction target resistor.

Systems, methods, and circuitries are provided for calibrating a heater used to heat an adjustable resistance network during a trimming procedure. In one example, a circuit is provided that includes an adjustable resistance network including first resistance segments; a heater element thermally coupled to the adjustable resistance network; a calibration resistor including second resistance segments thermally coupled to the first resistance segments; and interface circuitry coupled to the calibration resistor.

Systems and methods for sense resistors are disclosed. In one aspect, an integrated sense resistor includes a plurality of first metal bumps alternating with a plurality of second metal bumps in at least a first lateral direction and a plurality of thin film resistors each disposed between and electrically connected to a pair of adjacent ones of first and second metal bumps. The integrated sense resistor can be configured for sensing a voltage developed by current flowing across the integrated sense resistor for determining a value of the current.

A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate, a first resistive element and a second resistive element over the semiconductor substrate. A topmost surface of the second resistive element is higher than a topmost surface of the first resistive element. The semiconductor device structure also includes a first conductive feature and a second conductive feature electrically connected to the first resistive element. The second resistive element is between and electrically isolated from the first conductive feature and the second conductive feature. The semiconductor device structure further includes a first dielectric layer surrounding the first conductive feature and the second conductive feature.

Provided is a voltage divider circuit having a small area and good accuracy of a division ratio. Among a plurality of resistors of the voltage divider circuit, each of resistors having a large resistance value, that is, resistors (1/4R, 1/2R, 1R, 9R, 10R) having high required accuracy of ratio includes first unit resistors (5A) that have a first resistance value and are connected in series or connected in parallel to each other, and each of resistors having a small resistance value, that is, resistors (1/16R, 1/8R) having low required accuracy of ratio includes second unit resistors (5B) that have a second resistance value smaller than the first resistance value and are connected in parallel to each other.