An integrated circuit comprises a semiconductor substrate having a surface. A lateral resistor is arranged in a first plane parallel to the surface of the substrate. A vertical reference resistor comprises a layer arranged in a second plane parallel to the surface of the substrate and deeper than the first plane. This layer is doped to promote current flow in the second plane. The vertical reference resistor further comprises a first trench and a second trench coupled between the layer and the surface of the substrate. The first and second trenches are arranged in a vertical direction orthogonal to the first and the second planes and are doped to impede current flow in the vertical direction. A cross-section of the first and second trenches is two-fold rotationally symmetric around the vertical direction, and the lateral resistor and the first and second trenches have the same temperature coefficient.

Systems, methods, and circuitries are provided for calibrating a heater used to heat an adjustable resistance network during a trimming procedure. In one example, a circuit is provided that includes an adjustable resistance network including first resistance segments; a heater element thermally coupled to the adjustable resistance network; a calibration resistor including second resistance segments thermally coupled to the first resistance segments; and interface circuitry coupled to the calibration resistor.

A bias current generator circuit includes a current path and a leakage control circuit. The current path is connected between a supply voltage and a ground level. The current path includes a transistor and a resistor. The transistor has a current channel connected in the current path. The resistor has an upper terminal and a lower terminal connected in the current path, and a well contact to allow a reverse leakage current of the resistor to flow through. The leakage control circuit is connected to the supply voltage. The leakage control circuit includes a driving transistor to provide a driving voltage to the well contact of the resistor, and to allow the reverse leakage current of the resistor to flow into the leakage control circuit.

An electronic circuit comprises a first resistor (1) and a second resistor (2). The first resistor comprises: a first sheet (10) of resistive material; and a first pair (11, 12) of conductive contacts, each arranged in electrical contact with the first sheet, and arranged such that a shortest resistive path in the first sheet between the first pair of contacts passes through the first sheet and has a length equal to a thickness (LI) of the first sheet. The second resistor comprises: a second sheet (20) of resistive material; and a second pair (21, 22) of conductive contacts, each arranged in electrical contact with the second sheet, and arranged such that a shortest resistive path (L2) in the second sheet between the second pair of contacts passes along at least a portion of a length of the second sheet.

In a method of manufacturing a semiconductor device, a fin structure, which includes a stacked layer of first semiconductor layers and second semiconductor layers disposed over a bottom fin structure and a hard mask layer over the stacked layer, is formed. An isolation insulating layer is formed. A sacrificial cladding layer is formed over at least sidewalls of the exposed hard mask layer and stacked layer. A first dielectric layer is formed. A second dielectric layer is formed over the first dielectric layer. The second dielectric layer is recessed. A third dielectric layer is formed on the recessed second dielectric layer. The third dielectric layer is partially removed to form a trench. A fourth dielectric layer is formed by filling the trench with a dielectric material, thereby forming a wall fin structure.

An integrated circuit includes a substrate layer and a resistor bank in a polysilicon layer disposed on the substrate layer. The resistor bank includes a plurality of resistor elements having a body portion extending in a longitudinal direction. A metal line is disposed in a metal layer above the polysilicon layer to extend transverse to the longitudinal direction and across the body portion of a group of the plurality of resistor elements, thereby forming a first region of the resistor bank and a second region of the resistor bank. The first region is separated from the second region by the metal line. A resistor device having a predetermined resistance includes a subset of the resistor elements in the group electrically coupled together in the second region. The resistor device also includes first and second terminals located in the same first or second region of the resistor bank.

A semiconductor device includes a first terminal, a second terminal positioned away from the first terminal, a first resistive segment coupled between the first terminal and the second terminal, a third terminal positioned away from the first terminal and the second terminal, a second resistive segment coupled between the second terminal and third terminal, a first floating plate disposed physically proximate the first resistive segment and including a first end coupled to one of the first terminal and the second terminal, and a second floating plate disposed physically proximate the second resistive segment and including a first end coupled to one of the second terminal and the third terminal.

A method of fabricating an integrated circuit (IC) includes forming a dielectric layer on a substrate having a plurality of the IC. A thin-film resistor (TFR) layer is deposited on the dielectric layer, and an underlayer (UL) including carbon is formed on the TFR layer. A hard mask layer including silicon is formed on the UL. Masked etching of the hard mask layer transfers a pattern of a photoresist layer onto the hard mask layer to form a hard mask layer pattern. Masked etching of the UL transfers the hard mask layer pattern onto the UL to form a UL pattern. Masked etching of the TFR layer transfers the UL pattern onto the TFR layer to form a TFR layer pattern including a matched pair of TFRs. The matched pair of TFRs are generally included in circuitry configured together for implementing at least one function.

This semiconductor device includes: a semiconductor substrate of a first conductive type; a first impurity layer of a second conductive type that is formed on a surface of the semiconductor substrate; a second impurity layer of the first conductive type that is formed to surround the first impurity layer on the surface of the semiconductor substrate; an insulating film that covers at least the first impurity layer; a first resistive element that is spiral-shaped and is provided on the insulating film; a second resistive element that is provided on an outer side of the first impurity layer in a planar view of the semiconductor substrate; and a first wiring that couples an end portion of the first resistive element on an outer peripheral side thereof and the second resistive element to each other.

A semiconductor device includes a transistor structure disposed over a substrate, a first interlayer dielectric (ILD) layer disposed over the transistor structure, a second ILD layer disposed over the first ILD layer, and a first resistor wire disposed on the second ILD layer, and a second resistor wire disposed on the second ILD layer. A sheet resistance of the first resistor wire is different from a sheet resistance of the second resistor wire.