A semiconductor component, in particular for a varactor, having at least one first semiconductor layer and a second semiconductor layer. At least two identical surface electrodes are arranged directly or indirectly on the second semiconductor layer facing away from the first semiconductor layer in order to form two anti-serially connected diodes. The surface electrodes are arranged in an interacting manner such that a load carrier zone which forms the common counter electrode for the surface electrodes is arranged in the first semiconductor layer at least in the operating state, and at least one control contact for controlling the potential of the load carrier zone is provided in a region of the load carrier zone on the second semiconductor layer face facing away from the first semiconductor layer. The load carrier zone produces a continuous electric connection from the counter electrode to the at least one control contact at least in the operating state, and the load carrier zone protrudes beyond the surface electrodes in a projection onto the rear face of the semiconductor component.

A device includes a field effect transistor (FET) integrated with at least a portion of a bipolar junction transistor (BJT), in which a back gate of the FET shares an electrical connection with a base of the BJT, and in which a reverse voltage can be applied to the back gate of the FET.

Various examples are provided for varactors (variable capacitors). Described are both simple and complex forms of variable capacitors and improvements thereof. The varactor can be sufficiently small (narrow) to be isolated on a chip as a single or plurality of devices. Devices may be expanded using multiple varactors. In addition, various varactors can further be improved by the inclusion of a thin material to reduce the resistance of the varactor device. Diodes may also be implemented using the disclosed forms.

A device includes a first capacitor and a second capacitor connected to the first capacitor in parallel. The first capacitor includes a semiconductor region and a first plurality of gate stacks. The first plurality of gate stacks comprise a plurality of gate dielectrics over and contacting the semiconductor region, and a plurality of gate electrodes over the plurality of gate dielectrics. The second capacitor includes an isolation region, a second plurality of gate stacks over the isolation region, and a plurality of conductive strips over the isolation region and parallel to the second plurality of gate stacks. The second plurality of gate stacks and the plurality of conductive strips are laid out alternatingly.

The present disclosure provides a semiconductor device and a method of manufacturing a semiconductor device. The semiconductor device comprises a substrate, a first gate electrode, a second gate electrode, a first doped region, a second doped region, a third doped region, and a first interconnection structure. The substrate comprises a well region of a first conductive type. The first and second gate electrodes are disposed on the substrate. The first, second, and third doped regions are embedded within the well region and are of the first conductive type. The first interconnection structure electrically connects the first gate electrode and the second gate electrode. The first doped region and the second doped region are disposed on opposite sides of the first gate electrode.

A device includes a first capacitor and a second capacitor connected to the first capacitor in parallel. The first capacitor includes a semiconductor region and a first plurality of gate stacks. The first plurality of gate stacks comprise a plurality of gate dielectrics over and contacting the semiconductor region, and a plurality of gate electrodes over the plurality of gate dielectrics. The second capacitor includes an isolation region, a second plurality of gate stacks over the isolation region, and a plurality of conductive strips over the isolation region and parallel to the second plurality of gate stacks. The second plurality of gate stacks and the plurality of conductive strips are laid out alternatingly.

A passive tunable integrated circuit (PTIC) having an electro-static discharge (ESD) protection circuit is disclosed. The ESD protection circuit includes at least one spark gap that has a breakdown voltage determined by design parameters. The at least one spark gaps are configured to route signals above a breakdown voltage to ground in order to protect a variable capacitor. The design parameters can be based on a material (Barium Strontium Titanate), a structure, and a fabrication process of the PTIC and further based on expected ESD signals for a mobile device application.

Subject matter disclosed herein may relate to programmable fabrics including correlated electron switch devices.

Various embodiments of the present disclosure are directed towards a method for forming a varactor comprising a reduced surface field (RESURF) region. The method includes forming a drift region having a first doping type within a substrate. A RESURF region having a second doping type is formed within the substrate such that the RESURF region is below the drift region. A gate structure is formed on the substrate. A pair of contact regions is formed within the substrate on opposing sides of the gate structure. The contact regions respectively abut the drift region and have the first doping type, and wherein the first doping type is opposite the second doping type.

Various embodiments of the present disclosure are directed towards a varactor comprising a reduced surface field (RESURF) region. In some embodiments, the varactor includes a drift region, a gate structure, a pair of contact regions, and a RESURF region. The drift region is within a substrate and has a first doping type. The gate structure overlies the drift region. The contact regions are within the substrate and overlie the drift region. Further, the contact regions have the first doping type. The gate structure is laterally sandwiched between the contact regions. The RESURF region is in the substrate, below the drift region, and has a second doping type. The second doping type is opposite the first doping type. The RESURF region aids in depleting the drift region under the gate structure, which decreases the minimum capacitance of the varactor and increases the tuning range of the varactor.