An eighth semiconductor portion is provided between the first semiconductor portion and the third semiconductor portion. The eighth semiconductor portion is of the second conductivity type, contacting the first semiconductor portion, and having a lower second-conductivity-type impurity concentration than the second semiconductor portion.

A diode includes a plurality of fins defined in a semiconductor substrate. An anode region is defined by a doped region in a first surface portion of each of the plurality of fins and in a second surface portion of the semiconductor substrate disposed between adjacent fins in the plurality of fins. The doped region includes a first dopant having a first conductivity type and is contiguous between the adjacent fins. A cathode region is defined by an inner portion of each of the plurality of fins positioned below and contacting the first surface portion and a third portion of the semiconductor substrate positioned below and contacting the second surface portion. The cathode region is contiguous and the dopants in the cathode region and anode region have opposite conductivity types. A junction is defined between the anode region and the cathode region. A first contact interfaces with the anode region.

A number of monolithic diode limiter semiconductor structures are described. The diode limiters can include a hybrid arrangement of diodes with different intrinsic regions, all formed over the same semiconductor substrate. In one example, a method of manufacture of a monolithic diode limiter includes providing an N-type semiconductor substrate, providing an intrinsic layer on the N-type semiconductor substrate, implanting a first P-type region to a first depth into the intrinsic layer, implanting a second P-type region to a second depth into the intrinsic layer, and forming at least one passive circuit element over the intrinsic layer. The method can also include forming an insulating layer on the intrinsic layer, forming a first opening in the insulating layer, and forming a second opening in the insulating layer. The method can also include implanting the first P-type region through the first opening and implanting the second P-type region through the second opening.

A semiconductor device includes a plurality of tunnel diodes, each of which includes a first semiconductor region of a first conductive type and a second semiconductor region of a second conductive type that is provided above the first semiconductor region, the second semiconductor region being a nanowire shape; an insulating film provided around a side surface of the second semiconductor region; a plurality of first electrodes, each coupled to the first semiconductor region; and a plurality of second electrodes, each coupled to the second semiconductor region, wherein the second electrode has a first surface that faces the side surface of the second semiconductor region across the insulating film, and a diameter of a second semiconductor region of a first tunnel diode of the plurality of tunnel diodes is different from a diameter of a second semiconductor region of a second tunnel diode.

According to an embodiment, a semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of the first conductivity type, a first metal portion, a third semiconductor region of a second conductivity type, a first electrode, a fourth semiconductor region of the second conductivity type, and a second electrode. The first semiconductor region includes a first portion and a second portion. The second semiconductor region is provided on the first semiconductor region. The third semiconductor region is provided on part of the second semiconductor region. The first metal portion is provided in the first semiconductor region. The third semiconductor region is positioned on the first portion. The fourth semiconductor region is provided on another part of the second semiconductor region. The fourth semiconductor region is separated from the third semiconductor region. The fourth semiconductor region is positioned on the second portion.

A semiconductor device includes a substrate, a first isolation structure, a second isolation structure and a dummy pattern. The substrate includes a first part surrounding a second part at a top view. The first isolation structure is disposed between the first part and the second part, to isolate the first part from the second part. The second isolation structure is disposed at at least one corner of the first part. The dummy pattern is disposed on the second isolation structure. The present invention also provides a method of forming said semiconductor device.

An exemplary embodiment of the present disclosure provides a detector configured to output a signal associated with one or more interactions with subatomic particles. The detector comprises a sensor comprising a first diode comprising first semiconductor material abutting a first metal and forming a first junction, wherein the sensor is configured to be exposed to subatomic particles and a voltage reference member configured to generate a reference measurement. The sensor and the voltage reference member form a bandgap reference circuit. The present disclosure also provides methods for detecting subatomic particles from a solid-state detector comprising a first Schottky diode in electrical communication with a reference voltage member comprising a parallel circuit of two or more second Schottky diodes, wherein the first Schottky diode is configured to be exposed to subatomic particles and the second Schottky diodes of the reference voltage member are configured to generate a reference measurement.

A semiconductor device includes a composite pn-junction structure in a semiconductor substrate, wherein the composite pn-junction structure has a first junction grading coefficient m.sub.1, with m.sub.1≥0.50. The composite pn-junction structure includes a first partial pn-junction structure and a second partial pn-junction structure, wherein the first partial pn-junction structure has a first partial junction grading coefficient m.sub.11, and wherein the second partial pn-junction structure has a second partial junction grading coefficient m.sub.12. The first partial junction grading coefficient m.sub.11 is different to the second partial junction grading coefficient m.sub.12, with m.sub.11≠m.sub.12. At least one of the first and second partial junction grading coefficients m.sub.11, m.sub.12 is greater than 0.50, with m.sub.11 and/or m.sub.12>0.50. The first junction grading coefficient m.sub.1 of the composite pn-junction structure is based on a combination of the first and second partial junction grading coefficients m.sub.11, m.sub.12.

An electronic device is disclosed. The electronic device includes: a first doped region of a first doping type arranged in a first semiconductor layer of a second doping type complementary to the first doping type; an insulation layer formed on top of the first semiconductor layer and adjoining the first doped region; at least two active device regions arranged in a second semiconductor layer formed on top of the insulation layer; and an electrical connection between one of the at least two active device regions and the first doped region. Each of the at least two active device regions is arranged adjacent to the first doped region and separated from the first doped region by the insulation layer.

Integrated circuits including lateral diodes. In an example, diodes are formed with laterally neighboring source and drain regions (diffusion regions) configured with different polarity epitaxial growths (e.g., p-type and n-type), to provide an anode and cathode of the diode. In some such cases, dopants may be used in the channel region to create or otherwise enhance a PN or PIN junction between the diffusion regions and the semiconductor material of a channel region. The channel region can be, for instance, one or more nanoribbons or other such semiconductor bodies that extend between the oppositely-doped diffusion regions. In some cases, nanoribbons making up the channel region are left unreleased, thereby preserving greater volume through which diode current can flow. Other features include skipped epitaxial regions, elongated gate structures, using isolation structures in place of gate structures, and/or sub-fin conduction paths that are supplemental or alternative to a channel-based conduction paths.