Provided is a memory device including a delay circuit having gate insulation films with thicknesses different from each other. The memory device includes a delay circuit configured to input an input signal and output an output signal, and circuit blocks configured to control an operation of reading or writing memory cell data in response to the input signal or the output signal. One of transistors constituting a circuit block has a gate insulation film having such a thickness that an effect of negative biased temperature instability (NBTI) or positive biased temperature instability (PBTI) on the transistors is minimized. The delay circuit may be affected little by a shift in a threshold voltage that may be caused by NTBI or PBTI, and thus, achieve target delay time.

Methods of maintaining a state of a memory cell without interrupting access to the memory cell are provided, including applying a back bias to the cell to offset charge leakage out of a floating body of the cell, wherein a charge level of the floating body indicates a state of the memory cell; and accessing the cell.

A semiconductor memory instance is provided that includes an array of memory cells. The array includes a plurality of semiconductor memory cells arranged in at least one column and at least one row. Each of the semiconductor memory cells includes a floating body region configured to be charged to a level indicative of a state of the memory cell. Further includes are a plurality of buried well regions, wherein each of the buried well regions can be individually selected, and a decoder circuit to select at least one of the buried well regions.

Decoupling structures are provided. The decoupling structures may include first conductive patterns, second conductive patterns and a unitary supporting structure that structurally supports the first conductive patterns and the second conductive patterns. The decoupling structures may also include a common electrode disposed between ones of the first conductive patterns and between ones of the second conductive patterns. The first conductive patterns and the common electrode are electrodes of a first capacitor, and the second conductive patterns and the common electrode are electrodes of a second capacitor. The unitary supporting structure may include openings when viewed from a plan perspective. The first conductive patterns and the second conductive patterns are horizontally spaced apart from each other with a separation region therebetween, and none of the openings extend into the separation region.

A semiconductor device with a small variation in characteristics is provided. The semiconductor device includes an oxide, a first conductor and a second conductor over the oxide, a first insulator over the first conductor, a second insulator over the second conductor, a third conductor over the first insulator, a fourth insulator over the second insulator, a fifth insulator over the third insulator and the fourth insulator, a sixth insulator over the fifth insulator, a seventh insulator that is over the oxide and placed between the first conductor and the second conductor, an eighth insulator over the seventh insulator, a third conductor over the eighth insulator, and a ninth insulator over the third conductor and the sixth to eighth insulators. The third conductor includes a region overlapping the oxide. The seventh insulator includes a region in contact with each of the oxide, the first conductor, the second conductor, and the first to sixth insulators. The first insulator, the second insulator, the fifth insulator, and the ninth insulator are each a metal oxide having an amorphous structure.

Embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof. According to embodiments of the present disclosure, a height of the work function layer, especially a height of the second portion of the work function layer, is significantly increased, and a height of the first gate material layer is significantly reduced, so that the height ratio of the second portion of the work function layer to the first gate material layer to the second gate material layer is maintained at 3 to 8:1 to 1.5:1; therefore, it can be ensured that the work function of the WL groove filling material layer of the recessed gate structure with a small WL width will be significantly increased, thereby greatly weakening the row hammer effect at the bottom of the WL groove and obviously reducing the GIDL effect at the upper part of the WL groove.

Described herein are three-dimensional memory arrays that include multiple layers of memory cells. The layers are stacked and bonded to each other at bonding interfaces. The layers are formed on a support structure, such as a semiconductor wafer, that is grinded down before the layers are bonded. Vias extend through multiple layers of memory cells, including through the support structures and bonding interfaces. Thinning the support structure enables a tighter via pitch, which reduces the portion of the footprint used for vias. The memory cells may include three-dimensional transistors with a recessed gate and extended channel length.

A device structure includes transistors on a first level in a first region and a first plurality of capacitors on a second level, above the first level, where a first electrode of the individual ones of the first plurality of capacitors are coupled with a respective transistor. The device structure further includes a second plurality of capacitors on the second level in a second region adjacent the first region, where individual ones of the second plurality of capacitors include a second electrode, a third electrode and an insulator layer therebetween, where the second electrode of the individual ones of the plurality of capacitors are coupled with a first interconnect on a third level above the second level, and where the third electrode of the individual ones of the plurality of capacitors are coupled with a second interconnect.

A device structure includes a first interconnect line along a longitudinal direction and a second interconnect line parallel to the first interconnect line, where the first interconnect structure is within a first metallization level and the second interconnect line is within a second metallization level. A first transistor and a laterally separated second transistor are on a same plane above the second interconnect line, where a gate of the first transistor is coupled to the first interconnect line and a gate of the second transistor is coupled to the second interconnect line. A first capacitor is coupled to a first terminal of the first transistor and a second capacitor is coupled to a first terminal of the second transistor. A third interconnect line couples a second terminal of the first transistor with a second terminal of the second transistor.

Embodiments relate to a semiconductor structure, a memory structure and fabrication methods thereof. The semiconductor structure includes: a substrate, where a spacer is provided on the substrate, and a bit line structure is provided in the spacer and is at least partially exposed to the spacer; active area structures, where each of the active area structures includes an active pillar and a stress layer, the active pillar is positioned on the bit line structure, and the stress layer covers an exposed surface of the active pillar; each of the active area structure includes a first connection terminal, a second connection terminal, and a channel region positioned between the first connection terminal and the second connection terminal, and the first connection terminal is electrically connected to the bit line structure; and a word line structure covering a periphery of the channel region.