According to one embodiment, a semiconductor storage device includes a first memory cell, a second memory cell, a first transistor, a second transistor, and a third transistor. The first transistor includes a first portion electrically connected to a first circuit, a second portion electrically connected to the first memory cell, and a first gate electrode installed between the first portion and the second portion. The second transistor includes a third portion electrically connected to the first circuit, a fourth portion electrically connected to the second memory cell, and a first gate electrode installed between the third portion and the fourth portion. The third transistor includes the second portion, the fourth portion, a fifth portion electrically connected to a second circuit, and a second gate electrode installed between the second portion and the fifth portion and between the fourth portion and the fifth portion.

A semiconductor device includes a common source region formed in a semiconductor substrate, a bit line formed over the semiconductor substrate, first and second vertical channel layers coupled between the bit line and the common source region, wherein the first and second vertical channel layers are alternately arranged on the semiconductor substrate, first conductive layers stacked over the semiconductor substrate to surround one side of the first vertical channel layer, second conductive layers stacked over the semiconductor substrate to surround one side of the second vertical channel layer, and a charge storage layer formed between the first vertical channel layer and the first conductive layers and between the second vertical channel layer and the second conductive layers.

A three-dimensional semiconductor memory device is provided. A stacked structure is formed on a substrate. The stacked structure includes conductive patterns vertically stacked on the substrate. A selection structure including selection conductive patterns is stacked on the stacked structure. A channel structure penetrates the selection structure and the stacked structure to connect to the substrate. An upper interconnection line crosses the selection structure. A conductive pad is disposed on the channel structure to electrically connect the upper interconnection line to the channel structure. A bottom surface of the conductive pad is positioned below a top surface of the uppermost selection conductive pattern of the selection conductive patterns.

A method of fabricating a monolithic three dimensional memory structure is provided. The method includes forming a stack of alternating word line and dielectric layers above a substrate, forming a source line above the substrate, forming a memory hole extending through the alternating word line and dielectric layers and the source line, and forming a mechanical support element on the substrate adjacent to the memory hole.

A semiconductor memory device according to an embodiment, includes a plurality of semiconductor pillars extending in a first direction and being arranged along a second direction crossing the first direction, two interconnects extending in the second direction and being provided on two sides of the plurality of semiconductor pillars in a third direction crossing the first direction and the second direction, and an electrode film disposed between each of the semiconductor pillars and each of the interconnects. The two interconnects are drivable independently from each other.

A semiconductor memory device according to an embodiment, includes a semiconductor pillar extending in a first direction, a first electrode extending in a second direction crossing the first direction, a second electrode provided between the semiconductor pillar and the first electrode, a first insulating film provided between the semiconductor pillar and the second electrode, and a second insulating film provided between the first electrode and the second electrode. The second electrode includes a thin sheet portion disposed on the first electrode side, and a thick sheet portion disposed on the semiconductor pillar side. A length in the first direction of the thick sheet portion is longer than a length in the first direction of the thin sheet portion.

A semiconductor device according to an embodiment includes: a stacked body including a plurality of first conductive films stacked via an inter-layer insulating film;

a first conductive body contacting the stacked body to extend in a stacking direction; and a plurality of first insulating films in the same layers as the first conductive films and disposed between the first conductive body and the first conductive films, the first conductive body including a projecting part that projects along tops of one of the first insulating films and one of the first conductive films, and a side surface of the projecting part contacting an upper surface of the one of the first conductive films.

Semiconductor device includes a substrate, gate electrodes stacked and spaced apart from each other in a first direction perpendicular to an upper surface of the substrate, separation regions penetrating the gate electrodes, extending in a second direction perpendicular to the first direction, and spaced apart from each other in a third direction perpendicular to the first direction and the second direction, channel structures arranged in columns in the third direction and rows in the second direction and penetrating the gate electrodes between the separation regions, and bit lines extending in the third direction on the channel structures. The channel structures include a first group of channel structures repeatedly arranged and including three columns arranged with a first pitch and a second pitch smaller than the first pitch in order, and the bit lines are arranged with at least one pitch smaller than the second pitch in the second direction.

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, memory stack structures vertically extending through the alternating stack, a retro-stepped dielectric material portion overlying stepped surfaces of the alternating stack, a laterally perforated support pillar structure vertically extending through the alternating stack and the retro-stepped dielectric material portion, and a layer contact via structure laterally surrounded by the laterally perforated support pillar structure and contacting a top surface of a topmost electrically conductive layer within an area of the laterally perforated support pillar structure. Each electrically conductive layer within the area of the laterally perforated support pillar structure extends through the lateral openings.

According to one embodiment, a semiconductor memory device includes a substrate expanding in a first direction and a second direction, a plurality of conductive layers arranged in a third direction with a distance therebetween, the conductive layers including a first conductive layer, and each including a first portion and a second portion being arranged with the first portion in the second direction and including a terrace portion provided so as not to overlap an upper conductive layer in the third direction, a first insulating portion provided between the first portions and the second portions, and a first insulating layer arranged with the first portion of the first conductive layer in the second direction with the first insulating portion interposed therebetween.