A flash memory cell includes a rectifying device and a transistor. The rectifying device has an input end coupled to a bit line. The transistor has a charge storage structure. The transistor has a first end coupled to an output end of the rectifying device, the transistor has a second end coupled to a source line, and a control end of the transistor is coupled to a word line.

A control gate electrode and a memory gate electrode of a memory cell of a non-volatile memory are formed in a memory cell region of a semiconductor substrate, and a dummy gate electrode is formed in a peripheral circuit region. Then, n.sup.+-type semiconductor regions for a source or a drain of the memory cell are formed in the memory cell region and n.sup.+-type semiconductor regions for a source or a drain of MISFET are formed in the peripheral circuit region. Then, a metal silicide layer is formed over the n.sup.+-type semiconductor regions but the metal silicide layer is not formed over the control gate electrode, the memory gate electrode, and the gate electrode. Subsequently, the gate electrode is removed and replaced with the gate electrode for MISFET, Then, after removing the gate electrode and replacing it with a gate electrode for MISFET, a metal silicide layer is formed over the memory gate electrode and the control gate electrode.

A method of fabricating a monolithic three dimensional memory structure is provided. The method includes forming a stack of alternating word line and dielectric layers above a substrate, forming a source line above the substrate, forming a memory hole extending through the alternating word line and dielectric layers and the source line, and forming a mechanical support element on the substrate adjacent to the memory hole.

A method of manufacturing a semiconductor device includes forming a stack of alternating layers comprising insulating layers and spacer material layers over a substrate, forming a memory opening through the stack, forming a layer stack including a memory material layer, a tunneling dielectric layer, and a first semiconductor material layer in the memory opening, forming a protective layer over the first semiconductor channel layer, physically exposing a semiconductor surface underneath the layer stack by anisotropically etching horizontal portions of the protective layer and the layer stack at a bottom portion of the memory opening, removing a remaining portion of the protective layer selective to the first semiconductor channel layer, and forming a second semiconductor channel layer on the first semiconductor channel layer.

A semiconductor device according to an embodiment includes: a stacked body including a plurality of first conductive films stacked via an inter-layer insulating film;

a first conductive body contacting the stacked body to extend in a stacking direction; and a plurality of first insulating films in the same layers as the first conductive films and disposed between the first conductive body and the first conductive films, the first conductive body including a projecting part that projects along tops of one of the first insulating films and one of the first conductive films, and a side surface of the projecting part contacting an upper surface of the one of the first conductive films.

According to one embodiment, a semiconductor memory device includes a circuitry layer, first conductive layers, a pillar layer, and a second conductive layer. The circuitry layer is provided on a substrate and includes a CMOS circuit. The first conductive layers are provided above the circuitry layer, and are stacked with an insulation layer interposed therebetween. The pillar layer crosses the first conductive layers, and includes silicon single crystal. The second conductive layer is provided on the pillar layer and includes silicon single crystal containing impurities. The first conductive layers are provided between the circuitry layer and the second conductive layer.

A semiconductor device includes a substrate provided with a decoupling capacitor and plurality of circuit elements disposed along a first direction, and a plurality of first wiring line patterns disposed in a first wiring line layer over the substrate, including a power routing pattern coupled to the decoupling capacitor and a plurality of internal wiring line patterns coupled to the plurality of circuit elements. The plurality of first wiring line patterns extend in the first direction, and are aligned in conformity with virtual wiring line pattern tracks which are defined at a first pitch along a second direction intersecting the first direction and parallel to the substrate.

A memory device is disclosed. The disclosed memory device may include a first wafer, and a second wafer stacked on and bonded to the first wafer. The first wafer may include a cell structure including a memory cell array; and a first logic structure disposed under the cell structure, and including a column control circuit. The second wafer may include a second logic structure including a row control circuit.

A semiconductor device includes a lower level layer including a peripheral circuit; and an upper level layer provided on the lower level layer, the upper level layer including a vertically-extended memory cell string, wherein the lower level layer includes a first substrate; a device isolation layer defining a first active region of the first substrate; and a first gate structure including a first gate insulating pattern, a first conductive pattern, a first metal pattern, and a first capping pattern, which are sequentially stacked on the first active region, wherein the first conductive pattern comprises a doped semiconductor material, and the device isolation layer covers a first side surface of the first conductive pattern, and the first metal pattern includes a first body portion on the first conductive pattern.

A microelectronic device comprises a stack structure, contact structures, and additional contact structures. The stack structure comprises a vertically alternating sequence of conductive material and insulative material arranged in tiers. The stack structure is divided into blocks each comprising a stadium structure including steps comprising horizontal ends of the tiers. The contact structures are within a horizontal area of the stadium structure and vertically extend through the stack structure. The additional contact structures are on at least some of the steps of the stadium structure and are coupled to the contact structures. Memory devices and electronic devices are also disclosed.