Apparatuses and techniques are described for detecting and compensating for a set of memory cells having a slow program speed, based on a comparison between the number of program loops used to complete programming for different data states. A program loop (PL) number is stored when programming is completed for memory cells of each assigned data state. The PL number of an nth state is then compared to the PL number of another state such as the n−1st state. If the difference between the PL numbers exceeds a threshold, the set of memory cells is considered to be slow programming and a compensation is triggered. The compensation can involve increasing the program pulse width in each remaining program pulse of the program operation. In another approach, the compensation can be triggered and subsequently deactivated in the program operation.

According to one embodiment, a semiconductor storage device includes a first memory cell, a second memory cell, a first transistor, a second transistor, and a third transistor. The first transistor includes a first portion electrically connected to a first circuit, a second portion electrically connected to the first memory cell, and a first gate electrode installed between the first portion and the second portion. The second transistor includes a third portion electrically connected to the first circuit, a fourth portion electrically connected to the second memory cell, and a first gate electrode installed between the third portion and the fourth portion. The third transistor includes the second portion, the fourth portion, a fifth portion electrically connected to a second circuit, and a second gate electrode installed between the second portion and the fifth portion and between the fourth portion and the fifth portion.

A semiconductor device includes a common source region formed in a semiconductor substrate, a bit line formed over the semiconductor substrate, first and second vertical channel layers coupled between the bit line and the common source region, wherein the first and second vertical channel layers are alternately arranged on the semiconductor substrate, first conductive layers stacked over the semiconductor substrate to surround one side of the first vertical channel layer, second conductive layers stacked over the semiconductor substrate to surround one side of the second vertical channel layer, and a charge storage layer formed between the first vertical channel layer and the first conductive layers and between the second vertical channel layer and the second conductive layers.

A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.

A three-dimensional semiconductor memory device is provided. A stacked structure is formed on a substrate. The stacked structure includes conductive patterns vertically stacked on the substrate. A selection structure including selection conductive patterns is stacked on the stacked structure. A channel structure penetrates the selection structure and the stacked structure to connect to the substrate. An upper interconnection line crosses the selection structure. A conductive pad is disposed on the channel structure to electrically connect the upper interconnection line to the channel structure. A bottom surface of the conductive pad is positioned below a top surface of the uppermost selection conductive pattern of the selection conductive patterns.

A method of fabricating a monolithic three dimensional memory structure is provided. The method includes forming a stack of alternating word line and dielectric layers above a substrate, forming a source line above the substrate, forming a memory hole extending through the alternating word line and dielectric layers and the source line, and forming a mechanical support element on the substrate adjacent to the memory hole.

According to an embodiment, a semiconductor memory device includes a plurality of control gate electrodes, a semiconductor layer, and a charge accumulation layer. The plurality of control gate electrodes are provided as a stack above a substrate. The semiconductor layer has as its longitudinal direction a direction perpendicular to the substrate, and faces the plurality of control gate electrodes. The charge accumulation layer is positioned between the control gate electrode and the semiconductor layer. A lower end of the charge accumulation layer is positioned more upwardly than a lower end of a lowermost layer-positioned one of the control gate electrodes.

A method of manufacturing a semiconductor device includes forming a stack of alternating layers comprising insulating layers and spacer material layers over a substrate, forming a memory opening through the stack, forming a layer stack including a memory material layer, a tunneling dielectric layer, and a first semiconductor material layer in the memory opening, forming a protective layer over the first semiconductor channel layer, physically exposing a semiconductor surface underneath the layer stack by anisotropically etching horizontal portions of the protective layer and the layer stack at a bottom portion of the memory opening, removing a remaining portion of the protective layer selective to the first semiconductor channel layer, and forming a second semiconductor channel layer on the first semiconductor channel layer.

A semiconductor device according to an embodiment includes: a stacked body including a plurality of first conductive films stacked via an inter-layer insulating film;

a first conductive body contacting the stacked body to extend in a stacking direction; and a plurality of first insulating films in the same layers as the first conductive films and disposed between the first conductive body and the first conductive films, the first conductive body including a projecting part that projects along tops of one of the first insulating films and one of the first conductive films, and a side surface of the projecting part contacting an upper surface of the one of the first conductive films.

A semiconductor memory device includes a substrate with a cell array region and a connection region, an electrode structure including electrodes stacked on the substrate and having a staircase structure on the connection region, a vertical channel structure on the cell array region to penetrate the electrode structure and electrically connected to the substrate, a dummy structure on the connection region to penetrate the staircase structure, and a first sidewall oxide pattern interposed between the substrate and the dummy structure. The dummy structure includes an upper portion that is on the substrate, a middle portion that is in contact with the first sidewall oxide pattern, and a lower portion that is below the middle portion. With increasing vertical distance from the upper portion, a diameter of the middle portion decreases until it reaches its smallest value and then increases.