A display apparatus includes: a substrate; a first semiconductor layer disposed over the substrate; a first insulating layer disposed on the first semiconductor layer; a second insulating layer disposed on the first insulating layer; a first oxide material layer disposed between the substrate and the second insulating layer; and a first conductive layer disposed on the second insulating layer and electrically connected to the first semiconductor layer through a first contact hole defined in the first insulating layer, the second insulating layer, and the first oxide material layer.

A semiconductor device that has low power consumption and is capable of performing arithmetic operation is provided. The semiconductor device includes first to third circuits and first and second cells. The first cell includes a first transistor, and the second cell includes a second transistor. The first and second transistors operate in a subthreshold region. The first cell is electrically connected to the first circuit, the first cell is electrically connected to the second and third circuits, and the second cell is electrically connected to the second and third circuits. The first cell sets current flowing from the first circuit to the first transistor to a first current, and the second cell sets current flowing from the second circuit to the second transistor to a second current. At this time, a potential corresponding to the second current is input to the first cell. Then, a sensor included in the third circuit supplies a third current to change a potential of the second wiring, whereby the first cell outputs a fourth current corresponding to the first current and the amount of change in the potential.

A semiconductor device with a high on-state current is provided. An oxide semiconductor film; a source electrode and a drain electrode over the oxide semiconductor film; an interlayer insulating film positioned to cover the oxide semiconductor film, the source electrode, and the drain electrode; a gate insulating film over the oxide semiconductor film; a barrier insulating film over the oxide semiconductor film; and a gate electrode over the gate insulating film are included. The barrier insulating film is positioned between the source electrode and the gate insulating film and between the drain electrode and the gate electrode. An opening is formed in the interlayer insulating film so as to overlap with a region between the source electrode and the drain electrode. The barrier insulating film, the gate insulating film, and the gate electrode are positioned in the opening of the interlayer insulating film. Above the barrier insulating film, the gate insulating film is in contact with the interlayer insulating film.

Disclosed is a semiconductor device comprising an oxide semiconductor layer on a substrate and including a first part and a pair of second parts that are spaced apart from each other across the first part, a gate electrode on the first part of the oxide semiconductor layer, and a pair of electrodes on corresponding second parts of the oxide semiconductor layer. A first thickness of the first part of the oxide semiconductor layer is less than a second thickness of each second part of the oxide semiconductor layer. A number of oxygen vacancies in the first part of the oxide semiconductor layer is less than a number of oxygen vacancies in each second part of the oxide semiconductor layer.

A display device includes a substrate having a first surface and a second surface opposite to the first surface. The display device includes a first conductive layer disposed on the first surface and a second conductive layer disposed on the second surface. The first conductive layer and the second conductive layer are disposed on the opposite sides of the substrate. The display device includes a connective portion at least partially disposed in the substrate and penetrating from the first surface to the second surface. The first conductive layer is electrically connected to the second conductive layer through the connective portion. The display device includes a light-emitting element disposed on the first surface and an insulation layer disposed on the first conductive layer. Along a direction perpendicular to the first surface, the first electrode and the second electrode of the light-emitting element are not overlapped with the connective portion.

A semiconductor device with favorable electrical characteristics is provided. A semiconductor device with stable electrical characteristics is provided. A highly reliable semiconductor device is provided. A semiconductor layer is formed, a gate insulating layer is formed over the semiconductor layer, a metal oxide layer is formed over the gate insulating layer, and a gate electrode which overlaps with part of the semiconductor layer is formed over the metal oxide layer. Then, a first element is supplied through the metal oxide layer and the gate insulating layer to a region of the semiconductor layer that does not overlap with the gate electrode. Examples of the first element include phosphorus, boron, magnesium, aluminum, and silicon. The metal oxide layer may be processed after the first element is supplied to the semiconductor layer.

A transistor with small parasitic capacitance can be provided. A transistor with high frequency characteristics can be provided. A semiconductor device including the transistor can be provided. Provided is a transistor including an oxide semiconductor, a first conductor, a second conductor, a third conductor, a first insulator, and a second insulator. The first conductor has a first region where the first conductor overlaps with the oxide semiconductor with the first insulator positioned therebetween; a second region where the first conductor overlaps with the second conductor with the first and second insulators positioned therebetween; and a third region where the first conductor overlaps with the third conductor with the first and second insulators positioned therebetween. The oxide semiconductor including a fourth region where the oxide semiconductor is in contact with the second conductor; and a fifth region where the oxide semiconductor is in contact with the third conductor.

Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures, are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires and a second vertical arrangement of nanowires above a substrate, the first vertical arrangement of nanowires having a greater number of active nanowires than the second vertical arrangement of nanowires, and the first and second vertical arrangements of nanowires having co-planar uppermost nanowires. The integrated circuit structure also includes a first vertical arrangement of nanoribbons and a second vertical arrangement of nanoribbons above the substrate, the first vertical arrangement of nanoribbons having a greater number of active nanoribbons than the second vertical arrangement of nanoribbons, and the first and second vertical arrangements of nanoribbons having co-planar uppermost nanoribbons.

An active matrix substrate is provided with a plurality of oxide semiconductor TFTs including a plurality of first TFTs. An oxide semiconductor layer of each oxide semiconductor TFT includes a channel region, a source contact region, and a drain contact region. In a view from a normal direction of the substrate, the channel region is a region located between the source contact region and the drain contact region and overlapping a gate electrode, and the channel region includes a first end portion and a second end portion that oppose each other and extend in a first direction from the source contact region side toward the drain contact region side, a source side end portion that is located on the source contact region side of the first and second end portions and extends in a second direction that intersects the first direction, and a drain side end portion that is located on the drain contact region side of the first and second end portions and extends in the second direction. Each first TFT further includes a light blocking layer located between the oxide semiconductor layer and the substrate. In a view from the normal direction of the substrate, the light blocking layer includes an opening region that overlaps part of the channel region and a light blocking region that overlaps another part of the channel region. In a view from the normal direction of the substrate, the light blocking region includes a first light blocking portion that extends in the first direction over the first end portion of the channel region and a second light blocking portion that extends in the first direction over the second end portion of the channel region; each of the first light blocking portion and the second light blocking portion includes a first edge portion and a second edge portion that oppose each other and extend in the first direction; at least part of the first edge portion overlaps the channel region; and the second edge portion is located on an outer side of the channel region and does not overlap the channel region.

A display device includes pixels connected to scan lines and data lines intersecting the scan lines, wherein each of the pixels includes a light-emitting element, a driving transistor to control a driving current supplied to the light-emitting element according to a data voltage applied from the data lines, and a switching transistor to apply the data voltage of the data line to the driving transistor according to a scan signal applied from the scan lines. The driving transistor includes a first active layer having an oxide semiconductor and a first gate electrode below the first active layer. The switching transistor includes a second active layer having a same oxide semiconductor as the oxide semiconductor of the first active layer and a second gate electrode below the second active layer. At least one of the driving transistor and the switching transistor includes an oxide layer above each of the active layers.