Disclosed are a display device with integrated touch screen and a method of manufacturing the same, which prevent the partial detachment of an organic layer. The display device includes a light emitting device layer including a first electrode disposed on a first substrate, a light emitting layer disposed on the first electrode, and a second electrode disposed on the light emitting layer and a touch sensing layer disposed on the light emitting device layer. The touch sensing layer includes a first touch electrode layer, a second touch electrode layer, and a touch insulation layer disposed therebetween, and the touch insulation layer includes a touch inorganic layer covering the second touch electrode layer and a touch organic layer disposed on the touch inorganic layer.

Disclosed are a display device with integrated touch screen and a method of manufacturing the same, which prevent the partial detachment of an organic layer. The display device includes a light emitting device layer including a first electrode disposed on a first substrate, a light emitting layer disposed on the first electrode, and a second electrode disposed on the light emitting layer and a touch sensing layer disposed on the light emitting device layer. The touch sensing layer includes a first touch electrode layer, a second touch electrode layer, and a touch insulation layer disposed therebetween, and the touch insulation layer includes a touch inorganic layer covering the second touch electrode layer and a touch organic layer disposed on the touch inorganic layer.

After finishing of the front side CMOS manufacturing process, the silicon wafer is permanently bonded with its front side onto a carrier wafer. The carrier wafer is a high resistivity silicon wafer or a wafer of a dielectric or of a ceramic material. The silicon substrate of the device wafer is thinned from the back side such that the remaining silicon thickness is only a few micrometers. In the area dedicated to a spiral inductor, the substrate material is entirely removed by a masked etching process and the resulting gap is filled with a dielectric material. A spiral inductor coil is formed on the backside of the wafer on top of the dielectric material. The inductor coil is connected to the CMOS circuits on the front side by through-silicon vias.

Assemblies including a device layer of a silicon-on-insulator (SOI) substrate and a replacement substrate replacing a handle wafer of the SOI substrate, and methods for transferring the device layer of the SOI substrate from the handle wafer to the replacement substrate. A device structure is formed in a first section of the handle wafer, and a second section of the handle wafer adjoining the first section of the handle wafer is removed to expose a surface of the buried dielectric layer of the silicon-on-insulator substrate. A permanent substrate is attached to the surface of the buried dielectric layer. When the permanent substrate is attached to the surface of the buried dielectric layer, the section of the handle wafer is received inside a cavity defined in the permanent substrate.

Assemblies including a device layer of a silicon-on-insulator (SOI) substrate and a replacement substrate replacing a handle wafer of the SOI substrate, and methods for transferring the device layer of the SOI substrate from the handle wafer to the replacement substrate. A device structure is formed in a first section of the handle wafer, and a second section of the handle wafer adjoining the first section of the handle wafer is removed to expose a surface of the buried dielectric layer of the silicon-on-insulator substrate. A permanent substrate is attached to the surface of the buried dielectric layer. When the permanent substrate is attached to the surface of the buried dielectric layer, the section of the handle wafer is received inside a cavity defined in the permanent substrate.

Disclosed is a power storage element including a positive electrode current collector layer and a negative electrode current collector layer which are arranged on the same plane and can be formed through a simple process. The power storage element further includes a positive electrode active material layer on the positive electrode current collector layer; a negative electrode active material layer on the negative electrode current collector layer; and a solid electrolyte layer in contact with at least the positive electrode active material layer and the negative electrode active material layer. The positive electrode active material layer and the negative electrode active material layer are formed by oxidation treatment.

Disclosed is a power storage element including a positive electrode current collector layer and a negative electrode current collector layer which are arranged on the same plane and can be formed through a simple process. The power storage element further includes a positive electrode active material layer on the positive electrode current collector layer; a negative electrode active material layer on the negative electrode current collector layer; and a solid electrolyte layer in contact with at least the positive electrode active material layer and the negative electrode active material layer. The positive electrode active material layer and the negative electrode active material layer are formed by oxidation treatment.

An electronic circuit comprises a first resistor (1) and a second resistor (2). The first resistor comprises: a first sheet (10) of resistive material; and a first pair (11, 12) of conductive contacts, each arranged in electrical contact with the first sheet, and arranged such that a shortest resistive path in the first sheet between the first pair of contacts passes through the first sheet and has a length equal to a thickness (LI) of the first sheet. The second resistor comprises: a second sheet (20) of resistive material; and a second pair (21, 22) of conductive contacts, each arranged in electrical contact with the second sheet, and arranged such that a shortest resistive path (L2) in the second sheet between the second pair of contacts passes along at least a portion of a length of the second sheet.

An electronic circuit comprises a first resistor (1) and a second resistor (2). The first resistor comprises: a first sheet (10) of resistive material; and a first pair (11, 12) of conductive contacts, each arranged in electrical contact with the first sheet, and arranged such that a shortest resistive path in the first sheet between the first pair of contacts passes through the first sheet and has a length equal to a thickness (LI) of the first sheet. The second resistor comprises: a second sheet (20) of resistive material; and a second pair (21, 22) of conductive contacts, each arranged in electrical contact with the second sheet, and arranged such that a shortest resistive path (L2) in the second sheet between the second pair of contacts passes along at least a portion of a length of the second sheet.

The present disclosure provides an electronic device including a driving circuit substrate, a plurality of chips, and a passivation layer. The driving circuit substrate includes a plurality of active elements. The chips are disposed on the driving circuit substrate and electrically connected to the driving circuit substrate. The passivation layer covers the plurality of chips and the driving circuit substrate. The passivation layer has a first part on one of the plurality of chips and a second part on a part of the driving circuit substrate, the second part is not overlapped with the plurality of chips, and a first thickness of the first part is less than a second thickness of the second part. The first space between adjacent two of the plurality of chips is different from a second space between another adjacent two of the plurality of chips.