A chip component includes a substrate that has a first surface and a second surface on a side opposite to the first surface, a plurality of wall portions that are formed on a side of the first surface by using a part of the substrate, that have one end portion and one other end portion, and that are formed of a plurality of pillar units, a support portion that is formed around the wall portions by using a part of the substrate and that is connected to at least one of the end portion and the other end portion of the wall portions, and a capacitor portion formed by following a surface of the wall portion, in which each of the pillar units includes a central portion and three convex portions that extend from the central portion in three mutually different directions in a plan view and in which the wall portion is formed by a connection between the convex portions of the pillar units that adjoin each other.

A manufacturing method for a deep trench, the method includes forming a first trench in a substrate and performing a first cycle and a second cycle. Each comprising performing a passivation operation forming a passivation film on a sidewall and a bottom surface of the first trench, performing a first etching with a first bias power to remove the passivation film formed on the bottom surface of the first trench to expose the bottom surface of the first trench, and performing a second etching with a second bias power etching the exposed bottom surface of the first trench to form a second trench disposed below the first trench. The first bias power and the second bias power in the second cycle is greater than the first bias power and the second bias power in the first cycle, respectively.

A semiconductor device includes a landing pad and a capacitor disposed on and electrically connected to the landing pad. The capacitor includes a cylindrical bottom electrode, a dielectric layer and a top electrode. The cylindrical bottom electrode is disposed on an in contact with the landing pads, wherein an inner surface the cylindrical bottom electrode includes a plurality of protruding portions, and an outer surface of the cylindrical bottom electrode includes a plurality of concaved portions. The dielectric layer is conformally disposed on the inner surface and the outer surface of the cylindrical bottom electrode, and covering the protruding portions and the concaved portions. The top electrode is conformally disposed on the dielectric layer over the inner surface and the outer surface of the cylindrical bottom electrode.

A method of fabricating a semiconductor structure that includes: forming a first metal layer over a wafer; forming a second metal layer over the first metal layer; forming a first porous structure in a first region of the second metal layer located above a circuit area of the wafer and a second porous structure in a second region of the second metal layer located above a dicing area of the wafer, wherein the first porous structure includes a first set of pores, and wherein the second porous structure includes a second set of pores; forming a metal-insulator-metal stack in the first set of pores of the first porous structure; and etching the second set of pores of the second porous structure to expose the dicing area of the silicon wafer.

A semiconductor structure includes a substrate, comprising a first doped region; a first dielectric layer, located on the substrate; multiple deep trench capacitors, extending from the first dielectric layer to an inside of the substrate, in which each of the deep trench capacitors penetrates through the first doped region and comprises a serrated inner wall; multiple second doped regions, located in the substrate, in which each of the second doped regions surrounds a bottom of each deep trench capacitor and extends into the first doped region along an outer wall of the deep trench capacitor; and a first metal layer, located on the first dielectric layer and connected with the multiple deep trench capacitors.

An electronic system comprising a substrate with a substrate conductor pattern including substrate pads; a semiconductor component with active circuitry, and component pads coupled to the active circuitry of the semiconductor component and connected to the substrate pads of the substrate; a power source interface for receiving power from a power source; and a power distribution network for distributing power from the power source interface to the active circuitry of the semiconductor component. The power distribution network includes a first capacitor realized by conductive structures comprised in the semiconductor component, the first capacitor being coupled to a first component pad and a second component pad of the semiconductor component; a second capacitor arranged between the substrate and the semiconductor component, the second capacitor being coupled to the first component pad and the second component pad of the component package; and a power grid portion of the substrate conductor pattern.

A metal-insulator-metal (MIM) capacitor includes a substrate, a first metal layer, a deposition structure, a dielectric layer and a second metal layer. The first metal layer is disposed on the substrate and has a planarized surface. The deposition structure is disposed on the first metal layer, and at least a portion of the deposition structure extends into the planarized surface, wherein the first metal layer and the deposition structure have the same material. The dielectric layer is disposed on the deposition structure. The second metal layer is disposed on the dielectric layer.

A semiconductor device includes a substrate having a recess region, a first electrode in the recess region and having a three-dimensional network structure, a first dielectric layer in the recess region and covering the first electrode, a second electrode in the recess region and covering the first dielectric layer, and a molding layer filling a remaining portion of the recess region and covering the second electrode.

Integrated circuits with embedded memory that includes ferroelectric capacitors having first conductor structures coupled to an underlying array of access transistors, and second conductors coupled to independent plate lines that are shunted by a metal strap having a pitch similar to that of the capacitors. The independent plate lines may reduce bit-cell disturbs and/or simplify read/write process while the plate line straps reduce series resistance of the plate lines. The metal straps may be subtractively patterned lines in direct contact with the second capacitor conductors, or may be damascene structures coupled to the second capacitor conductors through vias that also have a pitch similar to that of the capacitors.

A semiconductor device includes a substrate. The semiconductor device further includes a first polysilicon structure over the substrate, wherein the first polysilicon structure has a first grain size. The semiconductor device further includes a first barrier layer over the first polysilicon structure, wherein the first barrier layer has a non-uniform thickness. The semiconductor device further includes a second polysilicon structure over the first barrier layer, wherein the second polysilicon structure has a second grain size smaller than the first grain size.