Decoupling structures are provided. The decoupling structures may include first conductive patterns, second conductive patterns and a unitary supporting structure that structurally supports the first conductive patterns and the second conductive patterns. The decoupling structures may also include a common electrode disposed between ones of the first conductive patterns and between ones of the second conductive patterns. The first conductive patterns and the common electrode are electrodes of a first capacitor, and the second conductive patterns and the common electrode are electrodes of a second capacitor. The unitary supporting structure may include openings when viewed from a plan perspective. The first conductive patterns and the second conductive patterns are horizontally spaced apart from each other with a separation region therebetween, and none of the openings extend into the separation region.

A metal capacitor provided includes a first metal layer and a second metal layer disposed above a substrate. The first metal layer includes a first electrode sheet and a second electrode sheet, and the second metal layer includes a third electrode sheet and a fourth electrode sheet. The first electrode sheet and the second electrode sheet collectively form a first coplanar capacitor. The third electrode sheet and the fourth electrode sheet collectively form a second coplanar capacitor. At least a portion of the fourth electrode sheet is arranged above the first electrode sheet, and the first electrode sheet and the fourth electrode sheet collectively form a first vertical capacitor. At least a portion of the third electrode sheet is arranged above the second electrode sheet, and the second electrode sheet and the third electrode sheet collectively form a second vertical capacitor.

The present disclosure relates to the technical field of semiconductors, and provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a substrate; a plurality of bottom electrodes, spaced apart from each other on the substrate; and a protective layer, located in upper portions of the bottom electrodes and separating the bottom electrodes. A material of the protective layer includes hard hydrogenated amorphous carbon.

Embodiments of the disclosure provide a semiconductor substrate, a method for forming same, and a layout structure. The method includes: providing a semiconductor structure including a first region and a second region arranged in sequence along a second direction, the second region including active structures arranged in an array along a first direction and a third direction, each of the active structure at least including a channel structure, the first direction, the second direction, and the third direction being perpendicular to each other, and the first direction and the second direction being parallel to a surface of the semiconductor substrate; forming a gate structure on a surface of the channel structure; and forming a word line structure extending in the first direction on the first region. The word line structure is connected with the gate structure located on the same layer.

The method for forming the capacitor stack structure includes: providing a substrate on which a plurality of first laminated structures arranged in a first direction and a first isolation structure located between every two adjacent the first laminated structures are formed, and the first laminated structure including first semiconductor layers and second semiconductor layers stacked alternately; forming, in the first laminated structures and the first isolation structures, first trench extending in the first direction, the spacing in a second direction between the adjacent remaining first semiconductor layers is greater than the spacing between the adjacent remaining second semiconductor layers; forming a support structure in the first trench, and removing the first semiconductor layers from the first laminated structure to form a first space; and forming capacitor structures in the first space to form a capacitor stack structure.

A method for forming a semiconductor structure includes the following: providing a semiconductor substrate, in which stack structures and isolation structures alternately arranged along a first direction are formed on the semiconductor substrate; forming a support structure in the stack structures and the isolation structures; etching the stack structures and the isolation structures to form multiple zigzag first semiconductor pillars in an array arrangement along the first direction and a second direction, in which an interspace is formed between the zigzag first semiconductor pillars; each zigzag first semiconductor pillar comprises first convex structures and first concave structures alternately arranged along a third direction, and is supported by the support structure; the first direction, the second direction and the third direction are perpendicular to one another, and the second direction is perpendicular to a top surface of the semiconductor substrate; forming capacitor structures the interspace.

The present disclosure provides a method of manufacturing a semiconductor structure, and a semiconductor structure. The method of manufacturing a semiconductor structure includes: providing an initial structure, wherein the initial structure includes a substrate, a laminated structure, and capacitor units, and the laminated structure includes support layers; forming a first mask layer, wherein the first mask layer covers a top surface of the laminated structure; forming a first opening in the first mask layer, wherein the first opening exposes the top surface of the laminated structure, and a projection region of the first opening on the substrate at least partially overlaps with projection regions of the capacitor units on the substrate; forming a shielding structure, wherein the shielding structure is located in the first opening, and the shielding structure covers a sidewall of the first opening.

Embodiments provide a method for fabricating an array structure of a columnar capacitor and a semiconductor structure, relating to the field of semiconductor manufacturing technology. In the method, before a mask layer is removed, a thickness of the mask layer in the peripheral region is first adjusted to be equal to a thickness of the mask layer in the array region, thereby avoiding damage to a top support layer caused by different thicknesses of the mask layer. Moreover, in the method, a thickness of the top support layer is increased by means of a supplementary support layer, to increase support strength of the top support layer, thereby further preventing occurrence of tilt of the columnar capacitor due to insufficient support strength of the top support layer.

The present application discloses a semiconductor device with a horizontally arranged capacitor. The semiconductor device includes a first palm portion positioned above a substrate; a second palm portion positioned above the substrate and opposite to the first palm portion; a first finger portion arranged substantially in parallel with a main surface of the substrate, positioned between the first palm portion and the second palm portion, and connecting to the first palm portion; a second finger portion arranged substantially in parallel with the first finger portion, positioned between the first palm portion and the second palm portion, and connecting to the second palm portion; a capacitor insulation layer positioned between the first finger portion and the second finger portion; a first spacer positioned between the first palm portion and second finger portion; and a second spacer positioned between the second palm portion and the first finger portion.

Various embodiments of the present disclosure provide a power device including at least one first conductive element adapted to generate a magnetic field when traversed by a current, and characterised in that it further comprises a Hall sensor electrically insulated from the first conductive element. The sensor and the first conductive element are mutually arranged so as to detect said magnetic field indicative of the current that traverses the first conductive element.