A light emitting display apparatus and a method of manufacturing the same are provided. The light emitting display apparatus includes a display panel including a display area and a non-display area, a first reference line arranged in a first direction in the display area, a second reference line arranged in a second direction transverse the first direction in the display area and electrically connected to the first reference line, and a power line arranged in the first direction in the display area and disposed between at least two of the first reference lines. A pattern density is reduced and a problem where a line interval increases is solved in implementing a narrow bezel and a large screen of a display panel on the basis of mesh-type reference lines provided in a display area and a power line disposed therebetween, and a problem where a second source voltage increases (EVSS rising) is minimized or reduced, thereby realizing a uniform image without a position-based luminance difference and a color coordinate difference.

A display device includes a first active pattern, a second active pattern spaced apart from the first active pattern in a plan view, a first connection pattern contacting the first active pattern, a second connection pattern contacting the second active pattern, a first pixel electrode, a second pixel electrode spaced apart from the first pixel electrode in the plan view, a common voltage pattern including a first protrusion portion protruding from a line portion in the plan view and overlapping the second connection pattern in a cross-sectional view, an emission layer disposed on the common voltage pattern, and a common electrode connecting the common voltage pattern.

A process of making sensors and sensor arrays that has the ability to manipulate of the morphology or flow of an applied drop or sample over the sensor array surface at any point in the patterning process and sensors and sensor arrays having increased sensitivity and limits of detection. In addition, said process can provided real time notification of any centerline deviation. Such production process can be adjusted in real time. Thus, large numbers of units can be made—even in millions of per day—with few if any out of specification units being produced. Such process does not require large-scale clean rooms and is easily configurable.

A process of making sensors and sensor arrays that has the ability to manipulate of the morphology or flow of an applied drop or sample over the sensor array surface at any point in the patterning process and sensors and sensor arrays having increased sensitivity and limits of detection. In addition, said process can provided real time notification of any centerline deviation. Such production process can be adjusted in real time. Thus, large numbers of units can be made—even in millions of per day—with few if any out of specification units being produced. Such process does not require large-scale clean rooms and is easily configurable.

A semiconductor device and a method of manufacturing the same are disclosed. The semiconductor device includes semiconductor wires disposed over a substrate, a source/drain epitaxial layer in contact with the semiconductor wires, a gate dielectric layer disposed on and wrapping around each channel region of the semiconductor wires, a gate electrode layer disposed on the gate dielectric layer and wrapping around the each channel region, and dielectric spacers disposed in recesses formed toward the source/drain epitaxial layer.

A display apparatus includes a substrate, a first data line in a display area, a first input line in a peripheral area, and a first connecting wire electrically connected to the first input line in a peripheral area of the substrate. The first connecting wire transfers a first input signal from the first input line to the first data line. The first connecting wire includes a first connecting line disposed in a display area of the substrate and extending in the first direction, and a second connecting line electrically connected to the first connecting line and extending in a second direction intersecting the first direction. The first connecting line and the second connecting line are disposed on different layers.

A transistor with small parasitic capacitance can be provided. A transistor with high frequency characteristics can be provided. A semiconductor device including the transistor can be provided. Provided is a transistor including an oxide semiconductor, a first conductor, a second conductor, a third conductor, a first insulator, and a second insulator. The first conductor has a first region where the first conductor overlaps with the oxide semiconductor with the first insulator positioned therebetween; a second region where the first conductor overlaps with the second conductor with the first and second insulators positioned therebetween; and a third region where the first conductor overlaps with the third conductor with the first and second insulators positioned therebetween. The oxide semiconductor including a fourth region where the oxide semiconductor is in contact with the second conductor; and a fifth region where the oxide semiconductor is in contact with the third conductor.

Methods of forming multi-tiered semiconductor devices are described, along with apparatus and systems that include them. In one such method, an opening is formed in a tier of semiconductor material and a tier of dielectric. A portion of the tier of semiconductor material exposed by the opening is processed so that the portion is doped differently than the remaining semiconductor material in the tier. At least substantially all of the remaining semiconductor material of the tier is removed, leaving the differently doped portion of the tier of semiconductor material as a charge storage structure. A tunneling dielectric is formed on a first surface of the charge storage structure and an intergate dielectric is formed on a second surface of the charge storage structure. Additional embodiments are also described.

Methods of forming multi-tiered semiconductor devices are described, along with apparatus and systems that include them. In one such method, an opening is formed in a tier of semiconductor material and a tier of dielectric. A portion of the tier of semiconductor material exposed by the opening is processed so that the portion is doped differently than the remaining semiconductor material in the tier. At least substantially all of the remaining semiconductor material of the tier is removed, leaving the differently doped portion of the tier of semiconductor material as a charge storage structure. A tunneling dielectric is formed on a first surface of the charge storage structure and an intergate dielectric is formed on a second surface of the charge storage structure. Additional embodiments are also described.

A diode is formed by a polycrystalline silicon bar which includes a first doped region with a first conductivity type, a second doped region with a second conductivity type and an intrinsic region between the first and second doped regions. A conductive layer extends parallel to the polycrystalline silicon bar and separated from the polycrystalline silicon bar by a dielectric layer. The conductive layer is configured to be biased by a bias voltage.