A microelectronic device includes a semiconductor substrate and a high voltage isolation capacitor over the substrate. The capacitor includes a bottom capacitor plate over the substrate. Dielectric layers are formed above the bottom capacitor plate, including a top dielectric layer. A high dielectric layer on the top dielectric layer includes at least a first sublayer having a first dielectric constant that is higher than a dielectric constant of the top dielectric layer. A top capacitor plate is formed on the high dielectric layer over the bottom capacitor plate. An electric field abatement structure surrounds the top capacitor plate. The electric field abatement structure includes a shelf of the high dielectric layer extending outward from a lower corner of the bottom capacitor plate at least 14 microns, and an isolation break in the high dielectric layer past the shelf, in which the first sublayer is removed from the isolation break.

A semiconductor device includes a substrate including a first active region, a second active region and a field region between the first and second active regions, and a gate structure formed on the substrate to cross the first active region, the second active region and the field region. The gate structure includes a p type metal gate electrode and an n-type metal gate electrode directly contacting each other, the p-type metal gate electrode extends from the first active region less than half way toward the second active region.

There is provided a semiconductor device including: a semiconductor layer including a main surface; a plurality of trenches including a plurality of first trench portions and a plurality of second trench portions, respectively; an insulating layer formed in an inner wall of each of the second trench portions; a first electrode buried in each of the second trench portions with the insulating layer interposed between the first electrode and each of the second trench portions; a plurality of insulators buried in the first trench portions so as to cover the first electrode; a contact hole formed at a region between the plurality of first trench portions in the semiconductor layer so as to expose the plurality of insulators; and a second electrode buried in the contact hole.

A semiconductor substrate is provided. A trench isolation region is formed in the semiconductor substrate. A resist pattern having an opening exposing the trench isolation region and partially exposing the semiconductor substrate is disposed adjacent to the trench isolation region. A first ion implantation process is performed to implant first dopants into the semiconductor substrate through the opening, thereby forming a well region in the semiconductor substrate. The trench isolation region is within the well region. A second ion implantation process is performed to implant second dopants into the semiconductor substrate through the opening, thereby forming an extended doped region contiguous with the well region. The resist pattern is then removed. After removing the resist pattern, a gate dielectric layer is formed on the semiconductor substrate. A gate is then formed on the gate dielectric layer. The gate overlaps with the extended doped region.

An apparatus including a substrate and a first nanosheet device located on the substrate. A second nanosheet device is located on the substrate, where the second nanosheet device is adjacent to the first nanosheet device. At least one first gate located on the first nanosheet device and the at least one first gate has a first width. At least one second gate located on the second nanosheet device and the at least one second gate has a second width. The first width and the second width are substantially the same. A diffusion break located between the first nanosheet device and the second nanosheet device. The diffusion break prevents the first nanosheet device from contacting the second nanosheet device, and the diffusion break has a third width. The third width is larger than the first width and the second width.

Embodiments of the disclosure provide a bipolar transistor structure with a collector on a polycrystalline isolation layer. A polycrystalline isolation layer may be on a substrate, and a collector layer may be on the polycrystalline isolation layer. The collector layer has a first doping type and includes a polycrystalline semiconductor. A base layer is on the collector layer and has a second doping type opposite the first doping type. An emitter layer is on the base layer and has the first doping type. A material composition of the doped collector region is different from a material composition of the base layer.

Methods and semiconductor devices are provided. A vertical junction field effect transistor (JFET) includes a substrate, an active region having a plurality of semiconductor fins, a source metal layer on an upper surface of the fins, a source metal pad layer coupled to the semiconductor fins through the source metal layer, a gate region surrounding the semiconductor fins, and a body diode surrounding the gate region.

A high withstand voltage isolation region has a first diffusion layer of a second conductivity type formed on a principal surface of a semiconductor substrate. The high withstand voltage MOS has a second diffusion layer of the second conductivity type formed on the principal surface of the semiconductor substrate. A low side circuit region has a third diffusion layer of a first conductivity type formed on the principal surface of the semiconductor substrate. A fourth diffusion layer of the first conductivity type having a higher impurity concentration than the semiconductor substrate is formed on the principal surface of the semiconductor substrate exposed between the first diffusion layer and the second diffusion layer. The fourth diffusion layer extends from the high side circuit region to the low side circuit region and does not contact the third diffusion layer.

A semiconductor device includes a substrate, first and second fins protruding from the substrate, and first and second source/drain (S/D) features over the first and second fins respectively. The semiconductor device further includes an isolation feature over the substrate and disposed between the first and second S/D features, and a dielectric layer disposed on sidewalls of the first and second S/D features and on sidewalls of the isolation feature. A top portion of the isolation feature extends above the dielectric layer.

An integrated circuit (IC) device includes a fin-type active region extending on a substrate in a first lateral direction. A gate line extends on the fin-type active region in a second lateral direction. The second lateral direction intersects the first lateral direction. A channel region is between the substrate and the gate line. A source/drain region is adjacent to the gate line on the fin-type active region and has a sidewall facing the channel region. A superlattice barrier is between the substrate and the channel region. The superlattice barrier is in contact with the source/drain region. The superlattice barrier has a structure in which a plurality of first sub-layers including a semiconductor layer doped with oxygen atoms and a plurality of second sub-layers including an undoped semiconductor layer are alternately stacked.