H01L29/0826

METHODS FOR FORMING BIPOLAR TRANSISTORS HAVING COLLECTOR WITH GRADING
20180012978 · 2018-01-11 ·

This disclosure relates to methods for forming bipolar transistors, such as heterojunction bipolar transistors, having at least one grading in the collector. In some embodiments, the methods include forming a sub-collector. In some embodiments the methods include forming a primary collector region with at least one grading having a doping concentration that decreases away from the sub-collector. In some embodiments the methods further include forming a secondary collector region to abut a base of the bipolar transistor and having a doping concentration of at least about 3×10.sup.16 cm.sup.−3 at an interface with the base. Such bipolar transistors can be implemented, for example, in power amplifiers.

Semiconductor device

On a single-crystal semiconductor substrate with an upper surface including a first direction in which an inverted mesa step extends and a second direction in which a forward mesa step extends in response to anisotropic etching in which an etching rate depends on crystal plane orientation, a bipolar transistor including a collector layer, a base layer, and an emitter layer that are epitaxially grown, and a base wire connected to the base layer are arranged. A step is provided at an edge of the base layer, and the base wire is extended from inside to outside of the base layer in a direction intersecting the first direction in a plan view. An intersection of the edge of the base layer and the base wire has a disconnection prevention structure that makes it difficult for step-caused disconnection of the base wire to occur.

Heterojunction bipolar transistor

A heterojunction bipolar transistor includes a collector layer, a base layer, and an emitter layer that are stacked on a substrate. The collector layer includes a graded semiconductor layer in which an electron affinity increases from a side closer to the base layer toward a side farther from the base layer. An electron affinity of the base layer at an interface closer to the collector layer is equal to an electron affinity of the graded semiconductor layer at an interface closer to the base layer.

Heterojunction bipolar transistor including ballast resistor and semiconductor device

A first sub-collector layer functions as an inflow path of a collector current that flows in a collector layer of a heterojunction bipolar transistor. A collector ballast resistor layer having a lower doping concentration than the first sub-collector layer is disposed between the collector layer and the first sub-collector layer.

SILICIDED COLLECTOR STRUCTURE
20220406906 · 2022-12-22 ·

A semiconductor device includes an emitter, a base, and a collector. A portion of the collector is located below a trench in a substrate. A collector silicide is located on at least a portion of a bottom portion of the trench and on at least a portion of a sidewall of the trench. The collector silicide structure is electrically coupled to a collector contact structure.

Semiconductor device

A bipolar transistor including a first collector layer, a second collector layer, a base layer, and an emitter layer is disposed on a substrate. Etching characteristics of the second collector layer are different from etching characteristics of the first collector layer and the base layer. In plan view, an edge of an interface between the first collector layer and the second collector layer is disposed inside an edge of a lower surface of the base layer, and an edge of an upper surface of the second collector layer coincides with the edge of the lower surface of the base layer or is disposed inside the edge of the lower surface of the base layer.

Silicided collector structure

A semiconductor device includes an emitter, a base, and a collector. A portion of the collector is located below a trench in a substrate. A collector silicide is located on at least a portion of a bottom portion of the trench and on at least a portion of a sidewall of the trench. The collector silicide structure is electrically coupled to a collector contact structure.

Fabrication of integrated circuit structures for bipolor transistors
09847408 · 2017-12-19 · ·

Methods of according to the present disclosure can include: providing a substrate including: a first semiconductor region, a second semiconductor region, and a trench isolation (TI) laterally between the first and second semiconductor regions; forming a seed layer on the TI and the second semiconductor region of the substrate, leaving the first semiconductor region of the substrate exposed; forming an epitaxial layer on the substrate and the seed layer, wherein the epitaxial layer includes: a first semiconductor base material positioned above the first semiconductor region of the substrate, and an extrinsic base region positioned above the seed layer; forming an opening within the extrinsic base material and the seed layer to expose an upper surface of the second semiconductor region; and forming a second semiconductor base material in the opening.

METHOD FOR MANUFACTURING A BIPOLAR JUNCTION TRANSISTOR
20170317198 · 2017-11-02 ·

Embodiments provide a method for manufacturing a bipolar junction transistor, comprising: providing a semiconductor substrate comprising a buried layer of a first conductive type; doping the semiconductor substrate in a collector implant region, to obtain a collector implant of the first conductive type extending parallel to a surface of the semiconductor substrate and from the surface of the semiconductor substrate to the buried layer; providing a base layer of a second conductive type on the surface of the semiconductor substrate, the base layer covering the collector implant; providing a sacrificial emitter structure on the base layer, wherein a projection of an area of the sacrificial emitter structure is enclosed by an area of the collector implant; and partially counter doping the collector implant through an area of the base layer surrounding an area of the base layer that is covered by the sacrificial emitter structure.

Integration of bipolar transistor into complimentary metal-oxide-semiconductor process

A fin heterojunction bipolar transistor (fin HBT) and a method of fabricating the fin HBT for integration with a fin complimentary metal-oxide-semiconductor (fin CMOS) into a BiCMOS fin device include forming a sub-collector layer on a substrate. The sub-collector layer includes silicon doped with arsenic (As+). A collector layer and base are patterned as fins along a first direction. An emitter layer is formed on the fins. The emitter layer is a continuous layer of epitaxially grown silicon. An oxide is deposited above the sub-collector layer, the base, and the emitter layer, and at least one contact is formed through the oxide to each of the sub-collector layer, the base, and the emitter layer.