Provided are a nitride semiconductor device and a manufacturing method thereof. The nitride semiconductor device includes a substrate, a first nitride semiconductor layer, a second nitride semiconductor layer, a first metal layer, a second metal layer and a dielectric layer. The first nitride semiconductor layer is disposed on the substrate. The second nitride semiconductor layer is disposed on the first nitride semiconductor layer. The first metal layer is disposed in the second nitride semiconductor layer. The second metal layer is disposed on the second nitride semiconductor layer. The dielectric layer is disposed between the first metal layer and the second nitride semiconductor layer and/or between the second metal layer and the second nitride semiconductor layer.

A vertical-mode tunnel field-effect transistor (TFET) is provided with an oxide region that may be laterally positioned relative to a source region. The oxide region operates to reduce a tunneling effect in a tunnel region underlying a drain region, during an OFF-state of the TFET. The reduction in tunneling effect results in a reduction or elimination of a flow of OFF-state leakage current between the source region and the drain region. The TFET may have components made from group III-V compound materials.

A method for manufacturing a semiconductor device includes forming a source and region in a substrate. A core channel region is formed adjacent the source region. A barrier layer is formed adjacent the core channel region. A drain region is formed in the substrate such that the barrier layer is between the core channel region and the drain region. A first portion of a shell is formed along the core channel region. A second portion of the shell is formed along the barrier layer. The second portion of the shell includes a different material than the first portion of the shell.

An apparatus comprising: a fermion source nanolayer (90); a first insulating nanolayer (92); a fermion transport nanolayer (94); a second insulating nanolayer (96); a fermion sink nanolayer (98); a first contact for applying a first voltage to the fermion source nanolayer; a second contact for applying a second voltage to the fermion sink nanolayer; and a transport contact for enabling an electric current via the fermion transport nanolayer. In a particular example, the apparatus comprises three graphene sheets (90, 94, 98) interleaved with two-dimensional Boron-Nitride (hBN) layers (92, 96).

Some embodiments of the disclosure provide a semiconductor device. The semiconductor device comprises: a substrate; a first nitride semiconductor layer on the substrate; a second nitride semiconductor layer on the first nitride semiconductor layer and having a band gap larger than a band gap of the first nitride semiconductor layer; an intermediate layer disposed on the second nitride semiconductor layer; and a conductive structure disposed on the intermediate layer, wherein a first even interface is formed between the intermediate layer and the second nitride semiconductor layer.

A field-effect transistor, including a source, drain and channel formed in a semiconductor layer a gate stack placed above the channel, including a metal electrode, a first layer of electrical insulator placed between the metal electrode and the channel, and a second layer of electrical insulator covering the metal electrode; a metal contact placed plumb with the source or drain and at least partially plumb with said gate stack; and a third layer of electrical insulator placed between said metal contact and said source or said drain.

A complementary logic device includes i) a substrate, ii) a first semiconductor device located on the substrate and including a first channel layer, a carrier supply layer for supplying a carrier to the channel layer, and an upper cladding layer and a lower cladding layer respectively located at upper and lower portions of the channel layer, iii) a second semiconductor device located on the substrate and including a structure the same or similar to that of the first semiconductor device, iv) a source electrode located on the two semiconductors and made of a ferromagnetic body, v) a drain electrode located on the two semiconductors and made of a ferromagnetic body, and vi) a gate electrode located on the two semiconductors and located between the two electrodes so that a gate voltage is applied thereto to control a spin of electrons passing through the two channel layers.

One illustrative transistor device disclosed herein includes a gate structure positioned above a semiconductor substrate and a source region and a drain region, each of which comprise an epi cavity with a bottom surface and a side surface. The transistor further includes an interface layer positioned on at least one of the side surface and the bottom surface of the epi cavity in each of the source/drain regions, wherein the interface layer comprises a non-semiconductor material and an epi semiconductor material positioned on at least an upper surface of the interface layer in the epi cavity in each of the source region and the drain region.

The present disclosure describes a semiconductor structure that includes a substrate from an undoped semiconductor material and a fin disposed on the substrate. The fin includes a non-polar top surface and two opposing first and second polar sidewall surfaces. The semiconductor structure further includes a polarization layer on the first polar sidewall surface, a doped semiconductor layer on the polarization layer, a dielectric layer on the doped semiconductor layer and on the second polar sidewall surface, and a gate electrode layer on the dielectric layer and the first polarized sidewall surface.

The magnetoresistive element includes a semiconductor channel layer, a pinned layer disposed on the semiconductor channel layer via a first tunnel layer, a free layer disposed on the semiconductor channel layer via a second tunnel layer, wherein the semiconductor channel layer includes a first region containing an interface with the first tunnel layer, a second region containing an interface with the second tunnel layer, and a third region, impurity concentrations in the first and second regions are higher than 1×10.sup.19 cm.sup.−3, an impurity concentration in the third region is 1×10.sup.19 cm.sup.−3 or less, the first and second regions are separated by the third region, and the impurity concentrations in the first and second regions decrease in the thickness direction of the semiconductor channel layer from the interface between the semiconductor channel layer and the first tunnel layer and the interface between the semiconductor channel layer and the second tunnel layer.