A thyristor includes a first transistor and a second transistor. The first transistor has a first end serving as an anode end. The second transistor has a control end coupled to a second end of the first transistor, a first end coupled to a control end of the first transistor, and a second end coupled to the first end of the second transistor and serving as a cathode end.

Substrate-less silicon controlled rectifier (SCR) integrated circuit structures, and methods of fabricating substrate-less silicon controlled rectifier (SCR) integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a first fin portion and a second fin portion that meet at a junction. A plurality of gate structures is over the first fin portion and a second fin portion. A plurality of P-type epitaxial structures and N-type epitaxial structures is between corresponding adjacent ones of the plurality of gate structures. Pairs of the P-type epitaxial structures alternate with pairs of the N-type epitaxial structures.

A thyristor includes a first transistor and a second transistor. The first transistor has a first end serving as an anode end. The second transistor has a control end coupled to a second end of the first transistor, a first end coupled to a control end of the first transistor, and a second end coupled to the first end of the second transistor and serving as a cathode end.

A method of writing data into a volatile thyristor memory cell array and maintaining the data with refresh is disclosed.

A method of writing data into a volatile thyristor memory cell array and maintaining the data with refresh is disclosed.

An ESD Protection Device includes a semiconductor body including a substrate, conductivity regions, and emitter and collector portions. Laterally adjacent first and second conductivity regions are arranged at least partially within the semiconductor body. The emitter and collector portions are disposed in contact with and arranged over the first and second conductivity regions respectively. The third conductivity region is disposed between the second conductivity region and the collector portion. The first and third conductivity regions have a first conductivity type. The second conductivity region, and the emitter and collector portions have a second conductivity type different from the first conductivity type. When an electrostatic discharge level exceeds a predetermined level, a first discharge current passes between the emitter portion and the collector portion through the first and second conductivity regions. A second discharge current subsequently occurs and passes between the first and third conductivity regions through the second conductivity region.

A method of writing data into a volatile thyristor memory cell array and maintaining the data with refresh is disclosed.

Operations with reduced current overall are performed on single thyristor memory cells forming a volatile memory cell cross-point array. A first voltage is applied across a first group of memory cells for the operation and a lower second voltage is applied across other groups of memory cells. The first voltage is then applied across a second group of memory cells while the second voltage is applied across the other groups including the first group of memory cells and repeated until the operations covers all the groups.

A method of writing data into a volatile thyristor memory cell array and maintaining the data with refresh is disclosed.

The present disclosure relates to four-layer latching devices having improved reverse current capabilities. The devices have a localized doping spike region in the upper base region, the lower base region, or both. The localized doping spike regions have a localized doping concentration that is greater than the doping concentration of the layer where the localized doping spike region is located. Within the base regions the localized spikes are located next to the corresponding upper emitter region, lower emitter region, or both.