A reverse conducting power semiconductor device includes a plurality of thyristor cells and a freewheeling diode are integrated in a semiconductor wafer. The freewheeling diode includes a diode anode layer, a diode anode electrode, a diode cathode layer, and a diode cathode electrode. The diode cathode layer includes diode cathode layer segments, each of which is stripe-shaped and arranged within a corresponding stripe-shaped first diode anode layer segment such that a longitudinal main axis of each diode cathode layer segment extends along the longitudinal main axis of the corresponding one of the first diode anode layer segments.

A gate-turn-off thyristor is provided. The gate-turn-off thyristor includes a plurality of strips formed by repeatedly arranging a plurality of N-type emitter regions with high doping concentration of an upper transistor on an upper surface of an N-type silicon substrate with high resistivity, wherein a periphery of each strip of the plurality of strips is surrounded with a P-type dense base region bus bar of the upper transistor, a cathode metal layer is disposed on an N-type emitter region of the plurality of N-type emitter regions of the upper transistor, and a P-type base region of the upper transistor is disposed below the N-type emitter region of the upper transistor; a side of the P-type base region of the upper transistor is connected to a P-type dense base region of the upper transistor or a P-type dense base region bus bar of the upper transistor.

A thyristor includes a first transistor and a second transistor. The first transistor has a first end serving as an anode end. The second transistor has a control end coupled to a second end of the first transistor, a first end coupled to a control end of the first transistor, and a second end coupled to the first end of the second transistor and serving as a cathode end.

Substrate-less silicon controlled rectifier (SCR) integrated circuit structures, and methods of fabricating substrate-less silicon controlled rectifier (SCR) integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a first fin portion and a second fin portion that meet at a junction. A plurality of gate structures is over the first fin portion and a second fin portion. A plurality of P-type epitaxial structures and N-type epitaxial structures is between corresponding adjacent ones of the plurality of gate structures. Pairs of the P-type epitaxial structures alternate with pairs of the N-type epitaxial structures.

A MOS controlled thyristor device according to the concept of the present invention includes a substrate comprising a first surface and a second surface, which face each other, gate patterns disposed on the first surface, a cathode electrode configured to cover the gate patterns, and an anode electrode disposed on the second surface, The substrate includes a lower emitter layer having a first conductive type, a lower base layer having a second conductive type on the lower emitter layer, an upper base region provided in an upper portion of the lower emitter layer and having a first conductive type, wherein the upper base region is configured to expose a portion of a top surface of the lower base layer, an upper emitter region having a second conductive type and provided in an upper portion of the upper base region, a first doped region having a first conductive type and a second doped region surrounded by the first doped region and having a second conductive type, wherein the first and second doped regions are provided in an upper portion of the upper emitter region, and a first doping pattern having a first conductive type, which is provided on one surface of the upper portion of the upper emitter region. The first doping pattern is interposed between the upper base region and the first doped region along a first direction parallel to the top surface of the substrate. The first doping pattern is configured to expose a top surface of the upper emitter region on the other surface of the upper portion of the upper emitter region. Each of the gate patterns is configured to cover portions of an exposed top surface of the lower base layer, an exposed top surface of the upper base layer, an exposed top surface of the upper emitter region, a top surface of the first doping pattern, and a top surface of the first doped region. The cathode electrode is configured to cover portions of top and side surfaces of the gate pattern, a top surface of the second doped region, and a top surface of the first doped region. The first conductive type and the second conductive type are different from each other.

An integrated gate-commutated thyristor (IGCT) includes a semiconductor wafer having a first main side and a second main side opposite to the first main side and a plurality of first type thyristor cells and second type thyristor cells. The cathode electrode of the first type thyristor cells forms an ohmic contact with the cathode region and the cathode electrode of the second type thyristor cells is insulated from the cathode region. A predefined percentage of second type thyristor cells of the overall amount of first type thyristor cells and second type thyristor cells in a segment ring is greater than .sub.0% and less than or equal to 75%.

A design technique is disclosed that divides up a cellular power switch into different size segments. Each segment is driven by a different driver circuit. The selection of the combination of segments is made to minimize the combined conduction and switching losses of the power switch. For example, for very light loads, switching losses dominate so only a small segment is activated for driving the load. For medium and high load currents, conduction losses become more significant, so additional segments are activated to minimize the total losses. In one embodiment, the number of cells in the segments is binary weighted, such as 1×, 2×, and 4×, so that there are seven different combinations of segments. The drivers may be configured to achieve the same or different slew rates of the segments, such as to reduce transients. The segments may all be in the same die or a plurality of dies.

A silicon carbide semiconductor device includes first semiconductor areas and second semiconductor areas. The first semiconductor areas have a first semiconductor layer of a second conductivity type, a second semiconductor layer of a first conductivity type, first semiconductor regions of the second conductivity type, second semiconductor regions of the first conductivity type, gate electrodes, and first electrodes. The second semiconductor areas have the first semiconductor layer, the second semiconductor layer, third semiconductor regions of the second conductivity type, the gate electrodes, and the first electrodes. The first semiconductor regions include low- impurity-concentration regions and high-impurity-concentration regions. The third semiconductor regions have a potential equal to that of the first electrodes. The first semiconductor regions are connected to the third semiconductor regions by MOS structures. In the first semiconductor regions, the high-impurity-concentration regions are provided at positions different from positions facing the first electrodes.

An insulated gate turn-off thyristor has a layered structure including a p+ layer (e.g., a substrate), an n-epi layer, a p-well, vertical insulated gate regions formed in the p-well, and an p-layer over the p-well and between the gate regions, so that vertical npn and pnp transistors are formed. The p-well has an intermediate highly doped portion. When the gate regions are sufficiently biased, an inversion layer surrounds the gate regions, causing the effective base of the npn transistor to be narrowed to increase its beta. When the product of the betas exceeds one, controlled latch-up of the thyristor is initiated. The p-well's highly doped intermediate region enables improvement in the npn transistor efficiency as well as enabling more independent control over the characteristics of the n-type layer (emitter), the emitter-base junction characteristics, and the overall dopant concentration and thickness of the p-type base.

A thyristor is formed from a vertical stack of first, second, third, and fourth semiconductor regions of alternated conductivity types. The fourth semiconductor region is interrupted in a gate area of the thyristor. The fourth semiconductor region is further interrupted in a continuous corridor that extends longitudinally from the gate area towards an outer lateral edge of the fourth semiconductor region. A gate metal layer extends over the gate area of the thyristor. A cathode metal layer extends over the fourth semiconductor region but not over the continuous corridor.