A tunnel field effect transistor includes a constant current formation layer, a source region and a drain region provided on the constant current formation layer, a channel layer provided between the source region and the drain region, a gate electrode provided on the channel layer, and a gate insulating film provided between the gate electrode and the channel layer, wherein the source region and the drain region have different conductivity types, and the constant current formation layer forms a constant current between the drain region and the constant current formation layer.

The present disclosure provides a semiconductor device, a manufacturing method, and electronic equipment. The semiconductor device comprising: a substrate; an interface, for generating two-dimensional charge carrier gas; a first electrode and a second electrode; and a first semiconductor layer of a first type doping formed on the substrate, wherein first regions and a second region are formed in the first semiconductor layer, wherein in the first regions, the dopant atoms of the first type do not have electrical activity, and in the second region, the dopant atoms of the first type have electrical activity; and the second region comprises a portion coplanar with the first regions. The semiconductor device can not only avoid damage to the crystal structure, but also can be easily realized in the processing, and it can maintain good transport properties of the two-dimensional charge carrier gas, which is beneficial to the improvement of device performance.

A stacked capacitor structure includes a MOS varactor and a stacked capacitor. The stacked capacitor is electrically connected to the MOS varactor. The MOS varactor includes a substrate, a gate, a first source/drain and a second source/drain. The substrate has a well, and the gate is positioned over the well. The first source/drain and the second source/drain are formed in the well and positioned at opposing sides of the gate. The stacked capacitor includes a plurality of metal layers. The metal layers are spaced from each other, stacked above the gate, and positioned below an inductive element.

A method of forming a semiconductor structure is provided. Trenches are formed in a first dielectric layer having a first height on a substrate. First III-V semiconductor patterns including aluminum are formed in the trenches to a second height lower than the first height. Second III-V semiconductor patterns are formed on the first III-V semiconductor patterns to a third height not higher than the first height to form fins including the first and second III-V semiconductor patterns. The first dielectric layer is completely removed to expose the fins. Selective oxidation is performed to oxidize the first III-V semiconductor patterns to form oxidized first III-V semiconductor patterns. Fin patterning is performed. A second dielectric layer is formed to cover the fins. The second dielectric layer is recessed to a level not higher than top surfaces of the oxidized first III-V semiconductor patterns. The semiconductor structure is also provided.

A semiconductor device includes a chip, a drain region, a source region formed at the surface layer portion of the main surface at a distance from the drain region, a channel inversion region formed on a side of the source region between the drain region and the source region in the surface layer portion of the main surface, a drift region formed in a region between the drain region and the channel inversion region in the surface layer portion of the main surface, a gate insulating film having a first portion that covers the channel inversion region on the main surface and a second portion that covers the drift region on the main surface, and a gate electrode having a first electrode portion covering the first portion and a second electrode portion led out from the first electrode portion onto second portion so as to partially expose second portion.

A method for forming a semiconductor device includes forming a mask layer with a first implantation window on a semiconductor substrate and implanting dopants with a first implantation energy into the semiconductor substrate through the first implantation window to form a first portion of a doping region of the semiconductor device. The mask layer is adapted to form a second implantation window of the mask layer. Further, dopants are implanted with a second implantation energy into the semiconductor substrate through the second implantation window. The second implantation energy differs from the first implantation energy and a lateral dimension of the first implantation window differs from a lateral dimension of the second implantation window.

A semiconductor device includes: semiconductor layer having first and second surfaces; first base region of first conductivity type formed in the semiconductor layer; second base region of second conductivity type adjacent to the first base region and formed in the semiconductor layer; first surface region of the second conductivity type selectively formed in the first base region; second surface region of the first conductivity type selectively formed in the second base region separate from the first base region; gate electrode facing portion of the first base region between boundary between the first and second base regions and the first surface region and portion of the second base region between the boundary and the second surface region, the gate electrode extending across the boundary; first and second electrodes connected to the first and second surface regions respectively; and third electrode connected in common to the first and second base regions.

A method of forming a semiconductor structure is provided. Trenches are formed in a first dielectric layer having a first height on a substrate. First III-V semiconductor patterns including aluminum are formed in the trenches to a second height lower than the first height. Second III-V semiconductor patterns are formed on the first III-V semiconductor patterns to a third height not higher than the first height to form fins including the first and second III-V semiconductor patterns. The first dielectric layer is completely removed to expose the fins. Selective oxidation is performed to oxidize the first III-V semiconductor patterns to form oxidized first III-V semiconductor patterns. Fin patterning is performed. A second dielectric layer is formed to cover the fins. The second dielectric layer is recessed to a level not higher than top surfaces of the oxidized first III-V semiconductor patterns. The semiconductor structure is also provided.

The lateral bipolar junction transistor has a silicon carbide layer, the silicon carbide layer comprises a base region with a first conductivity type, a collector region with a second conductivity type and an emitter region with a second conductivity type. The collector region and the emitter region are within the base region, and the base region, collector region and emitter region are all arranged along an upper surface of the silicon carbide layer.

A method of forming a semiconductor structure is provided. Trenches are formed in a first dielectric layer having a first height on a substrate. First III-V semiconductor patterns including aluminum are formed in the trenches to a second height lower than the first height. Second III-V semiconductor patterns are formed on the first III-V semiconductor patterns to a third height not higher than the first height to form fins including the first and second III-V semiconductor patterns. The first dielectric layer is completely removed to expose the fins. Selective oxidation is performed to oxidize the first III-V semiconductor patterns to form oxidized first III-V semiconductor patterns. Fin patterning is performed. A second dielectric layer is formed to cover the fins. The second dielectric layer is recessed to a level not higher than top surfaces of the oxidized first III-V semiconductor patterns. The semiconductor structure is also provided.