Disclosed are a semiconductor device and a manufacturing method therefor. The semiconductor device includes a semiconductor substrate, an epitaxial layer grown on a side of the semiconductor substrate; a quantum dot transport layer disposed on the epitaxial layer; and a gate oxide layer disposed on the quantum dot transport layer. With this arrangement, the semiconductor device provided by the present disclosure may reduce a threshold voltage while ensuring gate electrode reliability.

Provided are an optical sensor including graphene quantum dots and an image sensor including an optical sensing layer. The optical sensor may include a graphene quantum dot layer that includes a plurality of first graphene quantum dots bonded to a first functional group and a plurality of second graphene quantum dots bonded to a second functional group that is different from the first functional group. An absorption wavelength band of the optical sensor may be adjusted based on types of functional groups bonded to the respective graphene quantum dots and/or sizes of the graphene quantum dots.

The present disclosure provides a semiconductor structure, including: a substrate and a heterojunction structure disposed on the substrate, where the heterojunction structure includes a source region, a drain region, and a gate region disposed between the source region and the drain region, and the drain region is provided with a quantum well structure. The quantum well structure is provided in the drain region of the heterojunction structure, and the quantum well structure is used to generate photons by recombination luminescence, the photons can be radiated not only on the surface region of the potential barrier layer but also into the interior of the heterojunction structure, thereby the release process of electrons captured by the defects can be accelerated to reduce the current collapse effect as well as the dynamic on-resistance.

The present disclosure relates to semiconductor structures and, more particularly, to a heterojunction bipolar transistor and methods of manufacture. The structure includes: a sub-collector region; a collector region above the sub-collector region; an intrinsic base region composed of intrinsic base material located above the collector region; an emitter located above and separated from the intrinsic base material; and a raised extrinsic base having a stepped configuration and separated from and self-aligned to the emitter.

Using processes disclosed herein, materials and structures are created and used. For example, processes can include melting amorphous carbon doped with nitrogen and carbon-13 into an undercooled state followed by quenching. Materials disclosed herein may include dopants in concentrations exceeding thermodynamic solubility limits.

Embodiments of the invention include metal oxide metal field effect transistors (MOMFETs) and methods of making such devices. In embodiments, the MOMFET device includes a source and a drain with a channel disposed between the source and the drain. According to an embodiment, the channel has at least one confined dimension that produces a quantum confinement effect in the channel. In an embodiment, the MOMFET device also includes a gate electrode that is separated from the channel by a gate dielectric. According to embodiments, the band-gap energy of the channel may be modulated by changing the size of the channel, the material used for the channel, and/or the surface termination applied to the channel. Embodiments also include forming an type device and a P-type device by controlling the work-function of the source and drain relative to the conduction band and valance band energies of the channel.

An integrated circuit die includes a quad-gate device nanowire of channel material for a transistor (e.g., single material or stack to be a channel of a MOS device) formed by removing a portion of a sub-fin material from below the channel material, where the sub-fin material was grown in an aspect ration trapping (ART) trench. In some cases, in the formation of such nanowires, it is possible to remove the defective fin material or area under the channel. Such removal isolates the fin channel, removes the fin defects and leakage paths, and forms the nanowire of channel material having four exposed surfaces upon which gate material may be formed.

Quantum dot devices and related methods and systems that use semiconductor nanoribbons arranged in a grid where a plurality of first nanoribbons, substantially parallel to one another, intersect a plurality of second nanoribbons, also substantially parallel to one another but at an angle with respect to the first nanoribbons, are disclosed. Different gates at least partially wrap around individual portions of the first and second nanoribbons, and at least some of the gates are provided at intersections of the first and second nanoribbons. Unlike previous approaches to quantum dot formation and manipulation, nanoribbon-based quantum dot devices provide strong spatial localization of the quantum dots, good scalability in the number of quantum dots included in the device, and/or design flexibility in making electrical connections to the quantum dot devices to integrate the quantum dot devices in larger computing devices.

Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack and a plurality of linear arrays of gates above the quantum well stack to control quantum dot formation in the quantum well stack. An insulating material may be between a first linear array of gates and a second linear array of gates, the insulating material may be between individual gates in the first linear array of gates, and gate metal of the first linear array of gates may extend over the insulating material.

A semiconductor device includes a semiconductor substrate including a semiconductor element, a first surface-side electrode disposed on a first surface of the semiconductor substrate, and a second surface-side electrode disposed on a second surface of the semiconductor substrate. The semiconductor substrate includes a gallium nitride substrate and first column regions and second column regions disposed on a first principal surface of the gallium nitride substrate and alternately arranged along a c-axis direction in the first principal surface. The first column regions are formed of a first nitride semiconductor layer and the second column regions are formed of a second nitride semiconductor layer that is higher in band gap than the first nitride semiconductor layer. The semiconductor element is configured to enable a current to flow between the first surface and the second surface of the semiconductor substrate.