Disclosed herein are quantum dot devices and techniques. In some embodiments, a quantum computing processing device may include a quantum well stack, an array of quantum dot gate electrodes above the quantum well stack, and an associated array of selectors above the array of quantum dot gate electrodes. The array of quantum dot gate electrodes and the array of selectors may each be arranged in a grid.

A semiconductor stack for a Hall effect device, which comprises: a bottom barrier comprising Al.sub.xGa.sub.1-xAs, a channel comprising In.sub.yGa.sub.1-yAs, on the bottom barrier, a channel barrier with a thickness which is at least 2 nm and which is smaller than or equal to 15 nm, and which at least comprises a first layer comprising Al.sub.zGa.sub.1-zAs with 0.1≤z≤0.22, wherein the first layer has a thickness of at least 2 nm, wherein a conduction band edge of the bottom barrier and the first layer is higher than a conduction band edge of the channel, a doping layer comprising a composition of Al, Ga and As and doped with n-type material, a top barrier comprising a composition of Al, Ga and As.

Various systems, devices, articles and methods apply one or more luminescent defects disposed within a semiconductor body. A respective luminescent defect included in the one or more luminescent defects has a plurality of orbital states. An information processing device including a semiconductor body and one or more luminescent defects. A system including at least one processor and a quantum information processor comprising at least one luminescent defect. Methods for operation of devices and systems including one or more luminescent defects.

A semiconductor device having a GeSiSn base region combined with an emitter region and a collector region can be used to fabricate a bipolar transistor or a heterojunction bipolar transistor. The GeSiSn base region can be compositionally graded or latticed matched or strained to GaAs. The GeSiSn base region can be wafer bonded to a GaN or SiC collector region.

A quantum dot device is disclosed that includes a quantum well stack, a first and a second plunger gates above the quantum well stack, and a passive barrier element provided in a portion of the quantum well stack between the first and the second plunger gates. The passive barrier element may serve as means for localizing charge in the quantum dot device and may be used to replace charge localization control by means of a barrier gate. In general, a quantum dot device with a plurality of plunger gates provided over a given quantum well stack may include a respective passive barrier element between any, or all, of adjacent plunger gates in the manner as described for the first and second plunger gates.

Gate-controlled quantum dots based on silicon-germanium (SiGe) alloy heterostructures are provided. Also provided are quantum computing systems incorporating the gate-controlled quantum dots. The quantum dots are formed in a semiconductor heterostructure in which a SiGe alloy quantum well is sandwiched between SiGe alloy barriers or between Ge barriers. The presence of germanium in the quantum dots increases the average valley splitting for quantum dots confined in the SiGe. As a result, the yield of quantum dots having a sufficiently high valley splitting for device applications is increased by the use of a SiGe alloy in the quantum well.

A method for making a semiconductor device may include forming a first single crystal silicon layer having a first percentage of silicon 28, and forming a superlattice above the first single crystal silicon layer. The superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base silicon monolayers defining a base silicon portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base silicon portions. The method may further include forming a second single crystal silicon layer above the superlattice having a second percentage of silicon 28 higher than the first percentage of silicon 28.

A novel and useful quantum computing machine architecture that includes a classic computing core as well as a quantum computing core. A programmable pattern generator executes sequences of instructions that control the quantum core. In accordance with the sequences, a pulse generator functions to generate the control signals that are input to the quantum core to perform quantum operations. A partial readout of the quantum state in the quantum core is generated that is subsequently re-injected back into the quantum core to extend decoherence time. Access gates control movement of quantum particles in the quantum core. Errors are corrected from the partial readout before being re-injected back into the quantum core. Internal and external calibration loops calculate error syndromes and calibrate the control pulses input to the quantum core. Control of the quantum core is provided from an external support unit via the pattern generator or can be retrieved from classic memory where sequences of commands for the quantum core are stored a priori in the memory. A cryostat unit functions to provide several temperatures to the quantum machine including a temperature to cool the quantum computing core to approximately 4 Kelvin.

A quantum dot including a semiconductor nanocrystal core and a semiconductor nanocrystal shell disposed on the core and does not include cadmium, wherein the core includes a Group III-V compound, the quantum dot has a maximum photoluminescence peak in a green light wavelength region, a full width at half maximum (FWHM) of the maximum photoluminescence peak is less than about 50 nanometers (nm), and a difference between a wavelength of the maximum photoluminescence peak and a first absorption peak wavelength of the quantum dot is less than or equal to about 25 nanometers, and a production method thereof.

Various systems, devices, articles and methods related to one or more local luminescent defects disposed within semiconductor body including silicon. A respective defect included in the one or more defects supports a respective bound exciton. A respective pair of computational states is defined at the respective defect and one computational state of the pair of computational states includes a first configuration for the respective exciton. Information stored in the respective pair of computational states can be manipulated according to various systems, devices, articles and methods described herein.