A semiconductor device comprises a substrate, one or more first III-semiconductor layers, and a plurality of superlattice structures between the substrate and the one or more first layers. The plurality of superlattice structures comprises an initial superlattice structure and one or more further superlattice structures between the initial superlattice structure and the one or more first layers. The plurality of superlattice structures is configured such that a strain-thickness product of semiconductor layer pairs in each superlattice structure of the one or more further superlattice structures is greater than or equal to a strain-thickness product of semiconductor layer pairs in superlattice structure(s) of the plurality of superlattice structures between that superlattice structure and the substrate. The plurality of superlattice structures is also configured such that a strain-thickness product of semiconductor layer pairs in at least one of the one or more further superlattice structures is greater than a strain-thickness product of semiconductor layer pairs in the initial superlattice structure.

Embodiments of this disclosure relate to methods for removing a dummy material from under a superlattice structure. In some embodiments, after removing the dummy material, it is replaced with a bottom dielectric isolation layer beneath the superlattice structure.

Semiconductor devices and methods of manufacturing the same are described. The method includes forming a bottom dielectric isolation (BDI) layer on a substrate and depositing a template material in the source/drain trench. The template material is etched and then crystallized. Epitaxially growth of the source and drain regions then proceeds, with growth advantageously occurring on the bottom and sidewalls of the source and drain regions.

A method for making a semiconductor device may include forming a superlattice on a substrate comprising a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Moreover, forming at least one of the base semiconductor portions may include overgrowing the at least one base semiconductor portion and etching back the overgrown at least one base semiconductor portion.

In an embodiment, a substrate structure includes a support substrate, a buffer structure arranged on the support substrate, the buffer structure including an intentionally doped superlattice laminate, an unintentionally doped first Group III nitride layer arranged on the buffer structure, a second Group III nitride layer arranged on the first Group III nitride layer forming a heterojunction therebetween, and a blocking layer arranged between the heterojunction and the buffer structure. The blocking layer is configured to block charges from entering the buffer structure.

A method for making a semiconductor device may include forming a superlattice on a substrate comprising a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Moreover, forming at least one of the base semiconductor portions may include overgrowing the at least one base semiconductor portion and etching back the overgrown at least one base semiconductor portion.

A method for making a semiconductor device may include forming a superlattice on a substrate comprising a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Moreover, forming at least one of the base semiconductor portions may include overgrowing the at least one base semiconductor portion and etching back the overgrown at least one base semiconductor portion.

A tunnel field-effect transistor (TFET) includes a fin, an insulator layer, and at least one gate. The fin has a doped first region, a doped second region, and an interior region between the first region and the second region. The interior region is undoped or is more lightly doped than the first region and the second region. At least the interior region of the fin formed as a type II superlattice, wherein materials of the superlattice alternate vertically. The insulator layer is formed around the interior region. The gate is formed on at least a portion of the insulator region. The insulator layer and the at least one gate are configured to generate an inhomogeneous electrostatic potential within the interior region.

A method for making a semiconductor device may include forming a superlattice on a substrate comprising a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Moreover, forming at least one of the base semiconductor portions may include overgrowing the at least one base semiconductor portion and etching back the overgrown at least one base semiconductor portion.

A tunnel field-effect transistor (TFET) includes a fin, an insulator layer, and at least one gate. The fin has a doped first region, a doped second region, and an interior region between the first region and the second region. The interior region is undoped or is more lightly doped than the first region and the second region. At least the interior region of the fin formed as a type II superlattice, wherein materials of the superlattice alternate vertically. The insulator layer is formed around the interior region. The gate is formed on at least a portion of the insulator region. The insulator layer and the at least one gate are configured to generate an inhomogeneous electrostatic potential within the interior region.