A planar transistor device is disclosed including a gate structure positioned above a semiconductor substrate, the semiconductor substrate comprising a substantially planar upper surface, a channel region, a source region, a drain region, and at least one layer of a two-dimensional (2D) material that is positioned in at least one of the source region, the drain region or the channel region, wherein the layer of 2D material has a substantially planar upper surface, a substantially planar bottom surface and a substantially uniform vertical thickness across an entire length of the layer of 2D material in the gate length direction and across an entire width of the layer of 2D material in the gate width direction, wherein the substantially planar upper surface and the substantially planar bottom surface of the layer of 2D material are positioned approximately parallel to a substantially planar surface of the semiconductor substrate.

The present disclosure is directed to controlling charge transfer in 2D materials. A charge-transfer controlled 2D device comprises a 2D active conducting material, a 2D charge transfer source material, and at least one overlapping portion wherein the 2D active conducting material overlaps the 2D charge transfer source material including at least one edge of the 2D charge transfer source material.

An integrated circuit (IC) with a semiconductor device and an interconnect structure with carbon layers and methods of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a source/drain region on the fin structure, forming a contact structure on the S/D region, forming an oxide layer on the contact structure, forming a conductive carbon line within a first insulating carbon layer on the oxide layer, forming a second insulating carbon layer on the first insulating carbon layer, and forming a via within the second insulating carbon layer.

A system includes N-distant independent plasmonic graphene waveguides. The N-distant independent plasmonic graphene waveguides are used to generate an N-partite continuous variable entangled state.

A method for forming a semiconductor device includes providing a substrate structure, which has a semiconductor substrate and a semiconductor fin on the substrate. The method also includes forming a catalytic material layer overlying the semiconductor fins, and forming an isolation region covering the catalytic material layer in a lower portion of the semiconductor fins. Next, a graphene nanoribbon is formed on the catalytic material layer on an upper portion of the semiconductor fin, and a gate structure is formed on the graphene nanoribbon.

Provided is a method for synthesizing carbon agglomerates containing metastable carbyne/carbynoid chains; a method for synthesizing carbon or carbon compound allotropes from the agglomerates containing metastable carbyne/carbynoid chains; and the uses of the methods. The method for synthesizing carbon agglomerates containing metastable carbyne/carbynoid chains includes the following steps: a) forming carbon vapor precursors, containing carbine/carbynoid chains, by decomposing a carbon gas selected from among CH.sub.4, C.sub.2H.sub.2, C.sub.2H.sub.4, gaseous toluene, and benzene in the form of vapors at a temperature T such that 1 500° C.<T≦3 000° C.; and b) condensing the carbon vapor precursors, obtained in Step a), on the surface of a substrate, the temperature Ts of which is less than the temperature T. The invention is particularly of use in the field of electronics.

A transistor includes an oxide semiconductor layer, a source electrode and a drain electrode disposed spaced apart from each other on the oxide semiconductor layer, a gate electrode spaced apart from the oxide semiconductor layer, a gate insulating layer disposed between the oxide semiconductor layer and the gate electrode, and a graphene layer disposed between the gate electrode and the gate insulating layer and doped with a metal.

Method for making a porous graphene layer of a thickness of less than 100 nm with pores having an average size in the range of 5-900 nm, includes the following steps: providing a catalytically active substrate catalyzing graphene formation under chemical vapor deposition conditions, the catalytically active substrate in or on its surface being provided with a plurality of catalytically inactive domains having a size essentially corresponding to the size of the pores in the resultant porous graphene layer; chemical vapor deposition using a carbon source in the gas phase and formation of the porous graphene layer on the surface of the catalytically active substrate. The pores in the graphene layer are in situ formed due to the presence of the catalytically inactive domains.

A semiconductor device and method for forming the same. The device comprises at least a dielectric layer, a two-dimensional (2D) material layer, a gate structure, and source/drain contacts. The 2D material layer contacts the dielectric layer. The gate structure contacts the 2D material layer. The source/drain contacts are disposed above the 2D material layer and contact the gate structure. The method includes forming a structure including at least a handle wafer, a 2D material layer, a gate structure in contact with the 2D material layer, an insulating layer, and a sacrificial layer. A portion of the sacrificial layer is etched. An inter-layer dielectric is formed in contact with the insulating layer and sidewalls of the sacrificial layer. The sacrificial layer and a portion of the insulating layer are removed. Source and drain contacts are formed in contact with the portion of the 2D material layer.

A field effect transistor includes a substrate, a passivation layer on the substrate forming a passivated substrate, wherein the passivation layer is inert to XeF.sub.2, and a graphene lateral heterostructure field effect transistor (LHFET) on the passivated substrate.