Patent classifications
H01L29/18
Light emitting device
Each of a plurality of light emitting elements has a hexagonal shape with a center. An interior angle at each of corners is less than 180°. The plurality of light emitting elements include a first light emitting element having a first lateral side surface and a second light emitting element having a second lateral side surface. An orientation of the hexagonal shape of the second light emitting element is rotated by 30 degrees plus 30°+60°×N (N is an integer) with respect to the center of the second light emitting element relative to an orientation of the hexagonal shape of the first light emitting element such that the second lateral side surface is not parallel to the first lateral side surface.
Electronic device and method of manufacturing electronic device
The disclosure provides an electronic device and a method of manufacturing an electronic device. The electronic device includes a first substrate, a plurality of light-emitting dies, a transparent material layer, a sealing material, and a second substrate. The plurality of light-emitting dies are disposed on the first substrate. The transparent material layer is disposed on the first substrate. The sealing material is disposed on the first substrate and surrounds the transparent material layer. The second substrate is adhered to the first substrate through the transparent material layer and the sealing material.
Metal-semiconductor contact structure based on two-dimensional semimetal electrodes
Disclosed is a metal-semiconductor contact structure based on two-dimensional (2D) semimetal electrodes, including a semiconductor module and a metal electrode module, where the semiconductor module is a 2D semiconductor material, and the metal electrode module is a 2D semimetal material with no dangling bonds on its surface; the 2D semiconductor material and the 2D semimetal material are interfaced with a Van der Waals interface with a surface roughness of 0.01-1 nanometer (nm) and no dangling bonds on the surface, the 2D semiconductor material and the 2D semimetal material are spaced less than 1 nm apart.
Anodic oxide film for electric contact, optoelectronic display, and method of manufacturing optoelectronic display
The present invention relates generally to an anodic oxide film for electric contact, to an optoelectronic display, and to a method of manufacturing the optoelectronic display. More particularly, the present invention relates to an anodic oxide film for electric contact to electrically connect an optical element and a substrate in a position therebetween, to an optoelectronic display, and to a method of manufacturing the optoelectronic display.
Semiconductor memory device, chip ID generation method thereof and manufacturing method thereof
A semiconductor memory device includes programmable resistance memory cells and a controller which applies a forming pulse to first and second groups of the programmable resistance memory cells for inducing a change in the first group from an initial resistance range to an intermediate resistance range, and for inducing the second group having a resistance outside the intermediate range. When a forming rate is lower than a first forming threshold rate, the controller adjusts the forming pulse until the forming rate is higher than the first forming threshold rate. When a forming rate is higher than the first forming threshold rate but lower than a second forming threshold rate, the controller adjusts the forming pulse until the forming rate is higher than the second forming threshold rate. The controller applies a programming pulse to the first and second groups and generates a chip ID of the semiconductor memory device.
Semiconductor memory device, chip ID generation method thereof and manufacturing method thereof
A semiconductor memory device includes programmable resistance memory cells and a controller which applies a forming pulse to first and second groups of the programmable resistance memory cells for inducing a change in the first group from an initial resistance range to an intermediate resistance range, and for inducing the second group having a resistance outside the intermediate range. When a forming rate is lower than a first forming threshold rate, the controller adjusts the forming pulse until the forming rate is higher than the first forming threshold rate. When a forming rate is higher than the first forming threshold rate but lower than a second forming threshold rate, the controller adjusts the forming pulse until the forming rate is higher than the second forming threshold rate. The controller applies a programming pulse to the first and second groups and generates a chip ID of the semiconductor memory device.
HIGH PERFORMANCE THREE DIMENSIONALLY STACKED TRANSISTORS
A device including one or more transistors with nano sheets stacked along a vertical direction, and a method of fabricating the device are disclosed herein. In some embodiments, a device includes a transistor structure including at least a first dielectric nano sheet and a second dielectric nano sheet. The first dielectric nano sheet and the second dielectric nano sheet may extend parallel to a substrate. The second dielectric nano sheet may be disposed above the first dielectric nano sheet. The transistor may include a first source/drain structure coupled to a first end of the first dielectric nano sheet and a first end of the second dielectric nano sheet, and a second source/drain structure coupled to a second end of the first dielectric nano sheet and a second end of the second dielectric nano sheet.
HIGH PERFORMANCE THREE DIMENSIONALLY STACKED TRANSISTORS
A device including one or more transistors with nano sheets stacked along a vertical direction, and a method of fabricating the device are disclosed herein. In some embodiments, a device includes a transistor structure including at least a first dielectric nano sheet and a second dielectric nano sheet. The first dielectric nano sheet and the second dielectric nano sheet may extend parallel to a substrate. The second dielectric nano sheet may be disposed above the first dielectric nano sheet. The transistor may include a first source/drain structure coupled to a first end of the first dielectric nano sheet and a first end of the second dielectric nano sheet, and a second source/drain structure coupled to a second end of the first dielectric nano sheet and a second end of the second dielectric nano sheet.
Display device
A display device includes a substrate including a peripheral region folded back to face a rear surface of the substrate, and a counter region facing the peripheral region; and a filling member held between the peripheral region and the counter region. The substrate is folded such that the display device includes a first overlapping portion where a part of the peripheral region is bonded with the counter region with an adhesive material being provided therebetween; a second overlapping portion where a part of the peripheral region is in direct contact with the filling member; and a third overlapping portion where a part of the peripheral region is bonded with the filling member with an adhesive material being provided therebetween.
LED array
A method of fabricating and transferring a micro device and an array of micro devices to a receiving substrate are described. In an embodiment, an electrically insulating layer is utilized as an etch stop layer during etching of a p-n diode layer to form a plurality of micro p-n diodes. In an embodiment, an electrically conductive intermediate bonding layer is utilized during the formation and transfer of the micro devices to the receiving substrate.