An embodiment is a semiconductor device which includes a first oxide semiconductor layer over a substrate having an insulating surface and including a crystalline region formed by growth from a surface of the first oxide semiconductor layer toward an inside; a second oxide semiconductor layer over the first oxide semiconductor layer; a source electrode layer and a drain electrode layer which are in contact with the second oxide semiconductor layer; a gate insulating layer covering the second oxide semiconductor layer, the source electrode layer, and the drain electrode layer; and a gate electrode layer over the gate insulating layer and in a region overlapping with the second oxide semiconductor layer. The second oxide semiconductor layer is a layer including a crystal formed by growth from the crystalline region.

An embodiment is a semiconductor device which includes a first oxide semiconductor layer over a substrate having an insulating surface and including a crystalline region formed by growth from a surface of the first oxide semiconductor layer toward an inside; a second oxide semiconductor layer over the first oxide semiconductor layer; a source electrode layer and a drain electrode layer which are in contact with the second oxide semiconductor layer; a gate insulating layer covering the second oxide semiconductor layer, the source electrode layer, and the drain electrode layer; and a gate electrode layer over the gate insulating layer and in a region overlapping with the second oxide semiconductor layer. The second oxide semiconductor layer is a layer including a crystal formed by growth from the crystalline region.

A disclosed transistor structure includes a gate electrode, an active layer, a source electrode, a drain electrode, an insulating layer separating the gate electrode from the active layer, and a carrier modification device that reduces short channel effects by reducing carrier concentration variations in the active layer. The carrier modification device may include a capping layer in contact with the active layer that acts to increase a carrier concentration in the active layer. Alternatively, the carrier modification device may include a first injection layer in contact with the source electrode and the active layer separating the source electrode from the active layer, and a second injection layer in contact with the drain electrode and the active layer separating the drain electrode from the active layer. The first and second injection layers may act to reduce a carrier concentration within the active layer near the source electrode and the drain electrode.

A disclosed transistor structure includes a gate electrode, an active layer, a source electrode, a drain electrode, an insulating layer separating the gate electrode from the active layer, and a carrier modification device that reduces short channel effects by reducing carrier concentration variations in the active layer. The carrier modification device may include a capping layer in contact with the active layer that acts to increase a carrier concentration in the active layer. Alternatively, the carrier modification device may include a first injection layer in contact with the source electrode and the active layer separating the source electrode from the active layer, and a second injection layer in contact with the drain electrode and the active layer separating the drain electrode from the active layer. The first and second injection layers may act to reduce a carrier concentration within the active layer near the source electrode and the drain electrode.

A semiconductor memory device includes a substrate, memory layers, a first wiring disposed at a position closer to the substrate than memory layers or a position farther from the substrate than memory layers, a transistor layer disposed between memory layers and the first wiring, and a second wiring connected to the memory layers and the transistor layer. Each of memory layers includes a memory unit, a first semiconductor layer connected between the memory unit and the second wiring, a first electrode opposed to the first semiconductor layer, a third wiring connected to the first electrode, a second semiconductor layer electrically connected to one end portion of the third wiring, and a second electrode opposed to the second semiconductor layer. The transistor layer includes a third semiconductor layer connected between the first wiring and the second wiring, and a third electrode opposed to the third semiconductor layer.

A semiconductor memory device includes a substrate, memory layers, a first wiring disposed at a position closer to the substrate than memory layers or a position farther from the substrate than memory layers, a transistor layer disposed between memory layers and the first wiring, and a second wiring connected to the memory layers and the transistor layer. Each of memory layers includes a memory unit, a first semiconductor layer connected between the memory unit and the second wiring, a first electrode opposed to the first semiconductor layer, a third wiring connected to the first electrode, a second semiconductor layer electrically connected to one end portion of the third wiring, and a second electrode opposed to the second semiconductor layer. The transistor layer includes a third semiconductor layer connected between the first wiring and the second wiring, and a third electrode opposed to the third semiconductor layer.

Passivated semiconductor nanoparticles and methods for the fabrication and use of passivated semiconductor nanoparticles is provided herein.

Passivated semiconductor nanoparticles and methods for the fabrication and use of passivated semiconductor nanoparticles is provided herein.

A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a semiconductor channel layer, a gate structure, complex regions, a source terminal and a drain terminal. The gate structure is disposed on the semiconductor channel layer. The source terminal and the drain terminal are disposed on the semiconductor channel layer. The complex regions are respectively disposed between the source terminal and the semiconductor channel layer and between the drain terminal and the semiconductor channel layer.

A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a semiconductor channel layer, a gate structure, complex regions, a source terminal and a drain terminal. The gate structure is disposed on the semiconductor channel layer. The source terminal and the drain terminal are disposed on the semiconductor channel layer. The complex regions are respectively disposed between the source terminal and the semiconductor channel layer and between the drain terminal and the semiconductor channel layer.