A semiconductor device is provided. The semiconductor device includes a gate layer, a semiconductor layer and a ferroelectric layer disposed between the gate layer and the semiconductor layer. The semiconductor layer includes a first material containing a Group III element, a rare-earth element and a Group VI element, the ferroelectric layer includes a second material containing a Group III element, a rare-earth element and a Group V element and the gate layer includes a third material containing a Group III element and a rare-earth element. A method of fabricating a semiconductor device is also provided.

A semiconductor device is provided. The semiconductor device includes a gate layer, a semiconductor layer and a ferroelectric layer disposed between the gate layer and the semiconductor layer. The semiconductor layer includes a first material containing a Group III element, a rare-earth element and a Group VI element, the ferroelectric layer includes a second material containing a Group III element, a rare-earth element and a Group V element and the gate layer includes a third material containing a Group III element and a rare-earth element. A method of fabricating a semiconductor device is also provided.

A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a first transistor, a first resistive random access memory (RRAM) resistor, and a second RRAM resistor. The first resistor includes a first resistive material layer, a first electrode shared by the second resistor, and a second electrode. The second resistor includes the first electrode, a second resistive material layer, and a third electrode. The first electrode is electrically coupled to the first transistor.

Disclosed herein are IC structures, packages, and devices that include III-N transistors integrated on the same support structure as non-III-N transistors (e.g., Si-based transistors), using semiconductor regrowth. In one aspect, a non-III-N transistor may be integrated with an III-N transistor by depositing a III-N material, forming an opening in the III-N material, and epitaxially growing within the opening a semiconductor material other than the III-N material. Since the III-N material may serve as a foundation for forming III-N transistors, while the non-III-N material may serve as a foundation for forming non-III-N transistors, such an approach advantageously enables implementation of both types of transistors on a single support structure. Proposed integration may reduce costs and improve performance by enabling integrated digital logic solutions for III-N transistors and by reducing losses incurred when power is routed off chip in a multi-chip package.

Disclosed herein are IC structures, packages, and devices that include III-N transistors integrated on the same support structure as non-III-N transistors (e.g., Si-based transistors), using semiconductor regrowth. In one aspect, a non-III-N transistor may be integrated with an III-N transistor by depositing a III-N material, forming an opening in the III-N material, and epitaxially growing within the opening a semiconductor material other than the III-N material. Since the III-N material may serve as a foundation for forming III-N transistors, while the non-III-N material may serve as a foundation for forming non-III-N transistors, such an approach advantageously enables implementation of both types of transistors on a single support structure. Proposed integration may reduce costs and improve performance by enabling integrated digital logic solutions for III-N transistors and by reducing losses incurred when power is routed off chip in a multi-chip package.

A semiconductor device includes a first semiconductor well. The semiconductor device includes a channel structure disposed above the first semiconductor well and extending along a first lateral direction. The semiconductor device includes a gate structure extending along a second lateral direction and straddling the channel structure. The semiconductor device includes a first epitaxial structure disposed on a first side of the channel structure. The semiconductor device includes a second epitaxial structure disposed on a second side of the channel structure, the first side and second side opposite to each other in the first lateral direction. The first epitaxial structure is electrically coupled to the first semiconductor well with a second semiconductor well in the first semiconductor well, and the second epitaxial structure is electrically isolated from the first semiconductor well with a dielectric layer.

An object of the present invention is to provide a Schottky barrier diode less liable to cause dielectric breakdown due to concentration of an electric field. A Schottky barrier diode according to this disclosure includes a semiconductor substrate made of gallium oxide, a drift layer made of gallium oxide and provided on the semiconductor substrate, an anode electrode brought into Schottky contact with the drift layer, and a cathode electrode brought into ohmic contact with the semiconductor substrate. The drift layer has an outer peripheral trench surrounding the anode electrode in a plan view. The surface of the drift layer positioned between the anode electrode and the outer peripheral trench is covered with a semiconductor layer having a conductivity type opposite to that of the drift layer.

A method includes forming a semiconductive channel layer on a substrate. A dummy gate is formed on the semiconductive channel layer. Gate spacers are formed on opposite sides of the dummy gate. The dummy gate is removed to form a gate trench between the gate spacers, resulting in the semiconductive channel layer exposed in the gate trench. A semiconductive protection layer is deposited in the gate trench and on the exposed semiconductive channel layer. A top portion of the semiconductive protection layer is oxidized to form an oxidation layer over a remaining portion of the semiconductive protection layer. The oxidation layer is annealed after the top portion of the semiconductive protection layer is oxidized. A gate structure is formed over the semiconductive protection layer and in the gate trench after the oxidation layer is annealed.

A method includes forming a p-well and an n-well in a substrate. The method further includes forming a stack of interleaving first semiconductor layers and second semiconductor layers over the p-well and the n-well, the first semiconductor layers having a first thickness and the second semiconductor layers having a second thickness different than the first thickness. The method further includes annealing the stack of interleaving semiconductor layers. The method further includes patterning the stack to form fin-shaped structures including a first fin-shaped structure over the n-well and a second fin-shaped structure over the p-well. The method further includes etching to remove the second semiconductor layers from the first and second fin-shaped structures, where the first semiconductor layers have a different thickness within each of the first and second fin-shaped structures after the etching. The method further includes forming a metal gate over the first and second fin-shaped structures.

A high voltage transistor structure including a substrate, a first drift region, a second drift region, a first cap layer, a second cap layer, a gate structure, a first source and drain region, and a second source and drain region is provided. The first and second drift regions are disposed in the substrate. The first and second cap layers are respectively disposed on the first and second drift regions. The gate structure is disposed on the substrate and located over at least a portion of the first drift region and at least a portion of the second drift region. The first and second source and drain regions are respectively disposed in the first and second drift regions and located on two sides of the gate structure. The size of the first drift region and the size of the second drift region are asymmetric.