The present invention relates to various high quality n-type and p-type doped gallium-based semiconductor materials, electronic components incorporating these materials, and processes of producing these materials. In particular, The present invention relates processes to achieve high quality, uniform doping of a whole wafer or a thin layer of gallium-based semiconductor materials for various applications such as a vertical power transistor or diode.

A depletion-mode current source having a saturation current of sufficient accuracy for use as a pre-charge circuit in a start-up circuit of an AC-to-DC power converter is fabricated using an enhancement-mode-only process. The depletion-mode current source can be fabricated on the same integrated circuit (IC) as a gallium nitride field-effect transistor (FET) and resistive and capacitive components used in the start-up circuit, without affecting the enhancement-mode-only fabrication process by requiring additional masks or materials, as would be required to fabricate a depletion-mode FET on the same IC as an enhancement-mode FET. The current source includes a resistive patterned two-dimensional electron gas (2DEG) or two-dimensional hole gas (2DHG) channel coupled between two terminals and one or more metal field plates extending from one of the terminals and overlying the patterned area of the channel, the field plates being separated from the channel and from each other by dielectric layers.

A switching device including a GaN substrate; an unintentionally doped GaN layer on a first surface of the GaN substrate; a regrown unintentionally doped GaN layer on the unintentionally doped GaN layer; a regrowth interface between the unintentionally doped GaN layer and the regrown unintentionally doped GaN layer; a p-GaN layer on the regrown unintentionally doped GaN layer; a first electrode on the p-GaN layer; and a second electrode on a second surface of the GaN substrate.

An anti-fuse having two electrical connections is constructed by adding at least one zener diode and resistor to a power MOSFET. When the voltage across the two electrical connections exceeds the zener diode voltage and the maximum gate voltage of the MOSFET, the MOSFET burns out. This shorts out the device which can be used to bypass an LED or other load when that load burns out and forms an open circuit.

Techniques related to forming low defect density III-N films, device structures, and systems incorporating such films are discussed. Such techniques include epitaxially growing a first crystalline III-N structure within an opening of a first dielectric layer and extending onto the first dielectric layer, forming a second dielectric layer over the first dielectric layer and laterally adjacent to a portion of the first structure, and epitaxially growing a second crystalline III-N structure extending laterally onto a region of the second dielectric layer.

An integrated circuit structure includes a first semiconductor fin extending horizontally in a length direction and including a bottom portion and a top portion above the bottom portion, a bottom transistor associated with the bottom portion of the first semiconductor fin, a top transistor above the bottom transistor and associated with the top portion of the first semiconductor fin, and a first vertical diode. The first vertical diode includes: a bottom region associated with at least the bottom portion of the first semiconductor fin, the bottom region including one of n-type and p-type dopant; a top region associated with at least the top portion of the first semiconductor fin, the top region including the other of n-type and p-type dopant; a bottom terminal electrically connected to the bottom region; and a top terminal electrically connected to the top region at the top portion of the first semiconductor fin.

A stacked III-V semiconductor photonic device having a second metallic terminal contact layer at least formed in regions, a highly doped first semiconductor contact region of a first conductivity type, a very low doped absorption region of the first or second conductivity type having a layer thickness of 20 μm-2000 μm, a first metallic terminal contact layer, wherein the first semiconductor contact region extends into the absorption region in a trough shape, the second metallic terminal contact layer is integrally bonded to the first semiconductor contact region and the first metallic terminal contact layer is arranged below the absorption region. In addition, the stacked III-V semiconductor photonic device has a doped III-V semiconductor passivation layer of the first or second conductivity type, wherein the III-V semiconductor passivation layer is arranged at a first distance of at least 10 μm to the first semiconductor contact region.

A circuit element is formed on a substrate made of a compound semiconductor. A bonding pad is disposed on the circuit element so as to at least partially overlap the circuit element. The bonding pad includes a first metal film and a second metal film formed on the first metal film. A metal material of the second metal film has a higher Young's modulus than a metal material of the first metal film.

Disclosed are a diode and a manufacturing method thereof. The diode includes: a first substrate, the first substrate being an N-type doped substrate with a doping concentration equal to or greater than 1×10.sup.18 cm.sup.−3; a metal atomic layer located on a first surface of the first substrate; an epitaxial structure located on the metal atomic layer; a first electrode located on the epitaxial structure; and a second electrode located on a second surface, opposite to the first surface, of the first substrate. The diode significantly reduces forward conduction voltage drop.

When a nitride semiconductor layer into which impurity ions have been implanted is subjected to annealing after a protective film is provided on the nitride semiconductor layer, vacancy defects may be disadvantageously prevented from escaping outside through the surface of the nitride semiconductor layer and disappearing. A manufacturing method of a semiconductor device including a nitride semiconductor layer is provided. The manufacturing method includes implanting impurities into the nitride semiconductor layer, performing a first annealing on the nitride semiconductor layer at a first temperature within an atmosphere of a nitrogen atom containing gas without providing a protective film on the nitride semiconductor layer, forming the protective film on the nitride semiconductor layer after the first annealing, and after the protective film is formed, performing a second annealing on the nitride semiconductor layer at a second temperature that is higher than the first temperature.