Diodes employing one or more Group III-Nitride polarization junctions. A III-N polarization junction may include two III-N material layers having opposite crystal polarities. The opposing polarities may induce a two-dimensional charge sheet (e.g., 2D electron gas) within each of the two III-N material layers. Opposing crystal polarities may be induced through introduction of an intervening layer between two III-N material layers. The intervening layer may be of a material other than a Group III-Nitride. Where a P-i-N diode structure includes two Group III-Nitride polarization junctions, opposing crystal polarities at a first of such junctions may induce a 2D electron gas (2DEG), while opposing crystal polarities at a second of such junctions may induce a 2D hole gas (2DHG). Diode terminals may then couple to each of the 2DEG and 2DHG.

A terahertz module includes: a terahertz chip which includes an active device which emits a terahertz wave; and a dielectric substrate coupled to the terahertz chip. The terahertz chip includes a semiconductor substrate. The active device is disposed on an upper surface of the semiconductor substrate. A cutout is formed in a portion of a first side surface, among a plurality of side surfaces of the dielectric substrate, the cutout extending from an upper side of the first side surface to a lower side of the first side surface. The terahertz chip is fit into the cutout in such a direction that the upper surface of the semiconductor substrate is parallel to the first side surface and the semiconductor substrate is arranged in a bottom side of the cutout.

A group III nitride transistor structure capable of reducing a leakage current and a fabricating method thereof are provided. The group III nitride transistor structure includes: a first heterojunction and a second heterojunction which are laminated, wherein the first heterojunction is electrically isolated from the second heterojunction via a high resistance material and/or insertion layer; a first electrode, a second electrode and a first gate which are matched with the first heterojunction, wherein a third semiconductor is arranged between the first gate and the first heterojunction, and the first gate is also electrically connected with the first electrode; a source, a drain and a second gate which are matched with the second heterojunction, wherein the source and the drain are also respectively electrically connected with the first gate and the second electrode, and a sixth semiconductor is arranged between the second gate and the second heterojunction.

A resonant tunneling diode includes a substrate, and a mesa structure including a compound semiconductor layer including a heterojunction comprising a multi-barrier structure disposed on the substrate, and an electrode disposed on the upper surface of the compound semiconductor layer. An outer edge portion of the compound semiconductor layer is a first region including crystal defects, and the first region and the electrode are set apart from each other.

A diode structure and a method of fabrication of the diode structure is described. In one example, the diode structure is a PIN diode structure and includes an N-type layer formed on a substrate, an intrinsic layer formed on the N-type layer, and a P-type layer formed on the intrinsic layer. The P-type layer forms an anode of the diode structure, and the anode is formed as a quadrilateral-shaped anode. According to the embodiments, a top surface of the anode can be formed with one or more straight segments, such as a quadrilateral-shaped anode, to reduce at least one of a thermal resistance or an electrical on-resistance. These changes, among others, can improve the overall power handling capability of the PIN diode structure.

One or more systems, devices and/or methods provided herein relate to a device that can facilitate generation of a pulse to affect a qubit and to a method that can facilitate fabrication of a semiconductor device. The semiconductor device can comprise an RTD and an FET co-integrated in a common layer extending along a substrate. A method for fabricating the semiconductor device can comprise applying, at a substrate layer, a template structure comprising an opening, a cavity and a seed structure comprising a seed material and a seed surface, and sequentially growing along the substrate a plurality of diode layers of an RTD and a plurality of transistor layers of an FET within the cavity of the template structure from the seed surface, wherein the RTD and FET are co-integrated along the substrate.

The present disclosure provides a resonant tunneling diode and a manufacturing method thereof. The resonant tunneling diode includes: a first barrier layer; a second barrier layer; and a potential well layer between the first barrier layer and the second barrier layer, a material of the first barrier layer being Al.sub.xIn.sub.yN.sub.1-x-y, 1>x>0, 1>y>0, and/or a material of the second barrier layer being Al.sub.mIn.sub.nN.sub.1-m-n, 1>m>0, 1>n>0, and a material of the well layer including a gallium element.

A group III nitride transistor structure capable of reducing a leakage current and a fabricating method thereof are provided. The group III nitride transistor structure includes: a first heterojunction and a second heterojunction which are laminated, wherein the first heterojunction is electrically isolated from the second heterojunction via a high resistance material and/or insertion layer; a first electrode, a second electrode and a first gate which are matched with the first heterojunction, wherein a third semiconductor is arranged between the first gate and the first heterojunction, and the first gate is also electrically connected with the first electrode; a source, a drain and a second gate which are matched with the second heterojunction, wherein the source and the drain are also respectively electrically connected with the first gate and the second electrode, and a sixth semiconductor is arranged between the second gate and the second heterojunction.

The present disclosure provides a resonant tunneling diode including: a first barrier layer; a second barrier layer; a potential well layer between the first barrier layer and the second barrier layer, materials of the first barrier layer, the second barrier layer, and the potential well layer including a group III nitride, a material of the potential well layer including a gallium element; a first barrier layer between the first barrier layer and the potential well layer; and/or a second barrier layer between the second barrier layer and the potential well layer.

A nitride semiconductor device 1 includes a first transistor 3 which is constituted of a normally-off transistor and functions as a main transistor and a second transistor 4 which is constituted of a normally-on transistor and arranged to limit a gate current of the first transistor. The first transistor 3 includes a first electron transit layer 7A constituted of a nitride semiconductor and a first electron supply layer 8A which is formed on the first electron transit layer and constituted of a nitride semiconductor. The second transistor 4 includes a second electron transit layer 7B constituted of a nitride semiconductor and a second electron supply layer 8B which is formed on the second electron transit layer and constituted of a nitride semiconductor. A gate electrode 51 and a source electrode 44 of the second transistor 4 are electrically connected to a gate electrode 16 of the first transistor 3.