A bipolar transistor is supported by a substrate including a semiconductor layer overlying an insulating layer. A transistor base is formed by a base region in the semiconductor layer that is doped with a first conductivity type dopant at a first dopant concentration. The transistor emitter and collector are formed by regions doped with a second conductivity type dopant and located adjacent opposite sides of the base region. An extrinsic base includes an epitaxial semiconductor layer in contact with a top surface of the base region. The epitaxial semiconductor layer is doped with the first conductivity type dopant at a second dopant concentration greater than the first dopant concentration. Sidewall spacers on each side of the extrinsic base include an oxide liner on a side of the epitaxial semiconductor layer and the top surface of the base region.

A 3D integrated circuit device, including: a first transistor; a second transistor; and a third transistor, where the third transistor is overlaying the second transistor and the third transistor is controlled by a third control line, where the second transistor is overlaying the first transistor and the second transistor is controlled by a second control line, where the first transistor is part of a control circuit controlling the second control line and the third control line, and where the second transistor and the third transistor are self-aligned.

A digital circuit includes at least one quantum wire resonant tunneling transistor that includes an emitter terminal, a base terminal, a collector terminal, an emitter region in connection with the emitter terminal, a base region in connection with the base terminal, a collector region in connection with the collector terminal, an emitter barrier region between the emitter region and the base region, and a collector barrier region between the collector region and the base region. At least one of the emitter region, the base region, and the collector region includes a plurality of metal quantum wires.

A voltage tunable solar-blind UV detector using a EG/SiC heterojunction based Schottky emitter bipolar phototransistor with EG grown on p-SiC epi-layer using a chemically accelerated selective etching process of Si using TFS precursor.

A voltage tunable solar-blind UV detector using a EG/SiC heterojunction based Schottky emitter bipolar phototransistor with EG grown on p-SiC epi-layer using a chemically accelerated selective etching process of Si using TFS precursor.

A voltage tunable solar-blind UV detector using a EG/SiC heterojunction based Schottky emitter bipolar phototransistor with EG grown on p-SiC epi-layer using a chemically accelerated selective etching process of Si using TFS precursor.

A digital circuit includes at least one quantum wire resonant tunneling transistor that includes an emitter terminal, a base terminal, a collector terminal, an emitter region in connection with the emitter terminal, a base region in connection with the base terminal, a collector region in connection with the collector terminal, an emitter barrier region between the emitter region and the base region, and a collector barrier region between the collector region and the base region. At least one of the emitter region, the base region, and the collector region includes a plurality of metal quantum wires.

Schottky structure fabrication includes forming two trenches in a semiconductor material. The trenches are separated from each other by a mesa. Sidewalls and a bottom surface of the trenches are lined with a dielectric material. A conductive material is disposed in the trenches lining the dielectric material on the sidewalls and the bottom surface. The conductive material on the bottom surface of the trenches is removed so that a first portion of conductive material remains on a first sidewall of each trench, and a second portion of conductive material remains on a second sidewall of each trench. The first and second portions of conductive material are electrically isolated from each other. The space between the first and second portions of the conductive material is filled with a trench filling insulator material and a Schottky contact is formed between the outermost sidewalls of the two trenches.

A 3D integrated circuit device, including: a first transistor; a second transistor; and a third transistor, where the third transistor is overlaying the second transistor and the third transistor is controlled by a third control line, where the second transistor is overlaying the first transistor and the second transistor is controlled by a second control line, where the first transistor is part of a control circuit controlling the second control line and the third control line, and where the second transistor and the third transistor are self-aligned.