A semiconductor device and a method of forming the same are provided. The method includes forming a sacrificial gate structure over an active region. A first spacer layer is formed along sidewalls and a top surface of the sacrificial gate structure. A first protection layer is formed over the first spacer layer. A second spacer layer is formed over the first protection layer. A third spacer layer is formed over the second spacer layer. The sacrificial gate structure is replaced with a replacement gate structure. The second spacer layer is removed to form an air gap between the first protection layer and the third spacer layer.

Provided are a semiconductor device, a method of manufacturing the semiconductor device, and an electronic apparatus including the semiconductor device. According to the embodiments, the semiconductor device may include: a vertical structure extending in a vertical direction relative to a substrate; and a nanosheet extending from the vertical structure and spaced apart from the substrate in the vertical direction, wherein the nanosheet includes a first portion in a first orientation, and at least one of an upper surface and a lower surface of the first portion is not parallel to a horizontal surface of the substrate.

A semiconductor device and a method of forming the same are provided. The method includes forming a sacrificial gate structure over an active region. A first spacer layer is formed along sidewalls and a top surface of the sacrificial gate structure. A first protection layer is formed over the first spacer layer. A second spacer layer is formed over the first protection layer. A third spacer layer is formed over the second spacer layer. The sacrificial gate structure is replaced with a replacement gate structure. The second spacer layer is removed to form an air gap between the first protection layer and the third spacer layer.

A method includes forming an anti-punch-through layer over a first region and a second region of a substrate, forming a semiconductor layer over the anti-punch-through layer, patterning the semiconductor layer and the anti-punch-through layer to form a first plurality of fins over the first region and a second plurality of fins over the second region, and forming a patterned resist layer over the first plurality of fins and the second plurality of fins. The method also includes recessing a portion of the substrate between the first plurality of fins and the second plurality of fins in an etching process through openings of the patterned resist layer.

A device includes a semiconductor substrate having a first region and a second region. The device further includes a first pair of fin structures within the first region. The device further includes a second pair of fin structures within the second region. A top surface of the semiconductor surface between fin structures within the first pair is higher than a top surface of the semiconductor surface between the first pair and the second pair.

A trench MOSFET and a manufacturing method of the same are provided. The trench MOSFET includes a substrate, an epitaxial layer having a first conductive type, a gate in a trench in the epitaxial layer, a gate oxide layer, a source region having the first conductive type, and a body region and an anti-punch through region having a second conductive type. The anti-punch through region is located at an interface between the source region and the body region, and a doping concentration thereof is higher than that of the body region. The epitaxial layer has a first pn junction near the source region and a second pn junction near the substrate. N regions are divided into N equal portions between the two pn junctions, and N is an integer greater than 1. The closer the N regions are to the first pn junction, the greater the doping concentration thereof is.

A semiconductor device structure and a method for forming a semiconductor device structure are provided. The semiconductor device structure includes a stack of channel structures over a semiconductor fin and a gate stack wrapped around the channel structures. The semiconductor device structure also includes a source/drain epitaxial structure adjacent to the channel structures and an isolation structure surrounding the semiconductor fin. A protruding portion of the semiconductor fin protrudes from a top surface of the isolation structure. The semiconductor device structure further includes an embedded epitaxial structure adjacent to a first side surface of the protruding portion of the semiconductor fin.

A semiconductor device includes a substrate, a plurality of fins on the substrate, and an isolation region between the fins. Each of the fins includes a semiconductor material region and an impurity region disposed in the semiconductor material region. The impurity region has an upper surface below an upper surface of the isolation region.

A channel stop and well dopant migration control implant (e.g., of argon) can be used in the fabrication of a transistor (e.g., PMOS), either around the time of threshold voltage adjust and well implants prior to gate formation, or as a through-gate implant around the time of source/drain extension implants. With its implant depth targeted about at or less than the peak of the concentration of the dopant used for well and channel stop implants (e.g., phosphorus) and away from the substrate surface, the migration control implant suppresses the diffusion of the well and channel stop dopant to the surface region, a more retrograde concentration profile is achieved, and inter-transistor threshold voltage mismatch is improved without other side effects. A compensating through-gate threshold voltage adjust implant (e.g., of arsenic) or a threshold voltage adjust implant of increased dose can increase the magnitude of the threshold voltage to a desired level.

Nanostructure field-effect transistors (NSFETs) including isolation layers formed between epitaxial source/drain regions and semiconductor substrates and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a semiconductor substrate; a gate stack over the semiconductor substrate, the gate stack including a gate electrode and a gate dielectric layer; a first epitaxial source/drain region adjacent the gate stack; and a high-k dielectric layer extending between the semiconductor substrate and the first epitaxial source/drain region, the high-k dielectric layer contacting the first epitaxial source/drain region, the gate dielectric layer and the high-k dielectric layer including the same material.