The present disclosure provides a semiconductor device with void-free contacts and a method for preparing the semiconductor device. The semiconductor device includes a source/drain structure disposed over a semiconductor substrate, a dielectric layer disposed over the source/drain structure, and a conductive contact penetrating through the dielectric layer and the source/drain structure, wherein the conductive contact comprises a conductive layer and a barrier layer covering a sidewall and a bottom surface of the conductive layer. A first thickness of the harrier layer on the sidewall of the conductive layer is less than a second thickness of the barrier layer under the bottom surface of the conductive layer.

The present disclosure provides a semiconductor device with void-free contacts and a method for preparing the semiconductor device. The semiconductor device includes a source/drain structure disposed over a semiconductor substrate, a dielectric layer disposed over the source/drain structure, and a conductive contact penetrating through the dielectric layer and the source/drain structure, wherein the conductive contact comprises a conductive layer and a barrier layer covering a sidewall and a bottom surface of the conductive layer. A first thickness of the barrier layer on the sidewall of the conductive layer is less than a second thickness of the barrier layer under the bottom surface of the conductive layer.

Methods for forming contacts to source/drain regions and gate electrodes in low- and high-voltage devices and devices formed by the same are disclosed. In an embodiment a device includes a first channel region in a substrate adjacent a first source/drain region; a first gate over the first channel region; a second channel region in the substrate adjacent a second source/drain region, a top surface of the second channel region being below a top surface of the first channel region; a second gate over the second channel region; an ILD over the first gate and the second gate; a first contact extending through the ILD and coupled to the first source/drain region; and a second contact extending through the ILD, coupled to the second source/drain region, and having a width greater a width of the first contact and a height greater than a height of the first contact.

In an embodiment, a device includes: a dielectric fin on a substrate; a low-dimensional layer on the dielectric fin, the low-dimensional layer including a source/drain region and a channel region; a source/drain contact on the source/drain region; and a gate structure on the channel region adjacent the source/drain contact, the gate structure having a first width at a top of the gate structure, a second width at a middle of the gate structure, and a third width at a bottom of the gate structure, the second width being less than each of the first width and the third width.

A method of fabrication, including the steps for supplying a substrate including a layer of semiconductor material covered by a sacrificial gate including a sacrificial gate insulator including a middle part, and edges covered by sacrificial spacers and having a thickness tox; removal of the sacrificial gate insulator and the sacrificial gate material; formation of a conformal deposition of thickness thk of dielectric material inside of the groove formed in order to form a gate insulator, with tox>thk≧tox/2; formation of a gate electrode within the groove; removal of the sacrificial spacers so as to open up edges of the gate insulator layer; formation of spacers on the edges of the gate insulator layer on either side of the gate electrode, these spacers having a dielectric constant at the most equal to 3.5.

The present disclosure relate to a method to an integrated chip having a source/drain self-aligned contact to a transistor or other semiconductor device. In some embodiments, the integrated chip has a pair of gate structures including a gate electrode arranged over a substrate and an insulating material arranged over the gate electrode. A source/drain region is arranged within the substrate between the pair of gate structures. An etch stop layer is arranged along sidewalls of the pair of gate structures and over the source/drain region, and a dielectric layer is over the insulating material. A source/drain contact is arranged over the insulating material and the etch stop layer and is separated from the sidewalls of the pair of gate structures by the etch stop layer. The source/drain contact is electrically coupled to the source/drain region.

The present disclosure provides a semiconductor device with a profiled work-function metal gate electrode. The semiconductor structure includes a metal gate structure formed in an opening of an insulating layer. The metal gate structure includes a gate dielectric layer, a barrier layer, a work-function metal layer between the gate dielectric layer and the barrier layer and a work-function adjustment layer over the barrier layer, wherein the work-function metal has an ordered grain orientation. The present disclosure also provides a method of making a semiconductor device with a profiled work-function metal gate electrode.

The present disclosure provides a semiconductor device with a profiled work-function metal gate electrode. The semiconductor structure includes a metal gate structure formed in an opening of an insulating layer. The metal gate structure includes a gate dielectric layer, a barrier layer, a work-function metal layer between the gate dielectric layer and the barrier layer and a work-function adjustment layer over the barrier layer, wherein the work-function metal has an ordered grain orientation. The present disclosure also provides a method of making a semiconductor device with a profiled work-function metal gate electrode.

The present disclosure provides a semiconductor device with a profiled work-function metal gate electrode. The semiconductor structure includes a metal gate structure formed in an opening of an insulating layer. The metal gate structure includes a gate dielectric layer, a barrier layer, a work-function metal layer between the gate dielectric layer and the barrier layer and a work-function adjustment layer over the barrier layer, wherein the work-function metal has an ordered grain orientation. The present disclosure also provides a method of making a semiconductor device with a profiled work-function metal gate electrode.

Methods for forming contacts to source/drain regions and gate electrodes in low- and high-voltage devices and devices formed by the same are disclosed. In an embodiment a device includes a first channel region in a substrate adjacent a first source/drain region; a first gate over the first channel region; a second channel region in the substrate adjacent a second source/drain region, a top surface of the second channel region being below a top surface of the first channel region; a second gate over the second channel region; an ILD over the first gate and the second gate; a first contact extending through the ILD and coupled to the first source/drain region; and a second contact extending through the ILD, coupled to the second source/drain region, and having a width greater a width of the first contact and a height greater than a height of the first contact.