A semiconductor device 1 includes a base body 3 that includes a p type substrate 4 and an n type semiconductor layer 5 formed on the p type substrate 4 and includes an element region 2 having a transistor 40 with the n type semiconductor layer as a drain, a p type element isolation region 7 that is formed in a surface layer portion of the base body such as to demarcate the element region, and a conductive wiring 25 that is disposed on a peripheral edge portion of the element region and is electrically connected to the n type semiconductor layer. The transistor includes an n.sup.+ type drain contact region 14 that is formed in a surface layer portion of the n type semiconductor layer in the peripheral edge portion of the element region. The conductive wiring is disposed such as to cover at least a portion of an element termination region 30 between the n.sup.+ type drain contact region and the p type element isolation region.

A semiconductor device includes a semiconductor film and a gate structure on the semiconductor film. The gate structure includes a multi-stepped gate dielectric on the semiconductor film and a gate electrode on the multi-stepped gate dielectric. The multi-stepped gate dielectric includes a first gate dielectric segment having a first thickness and a second gate dielectric segment having a second thickness that is less than the first thickness.

A semiconductor device includes a semiconductor layer, a drift region, a source area, a well region, a drain area, and a dielectric film. The drift region and the source area are formed in the semiconductor layer. The well region is formed in the semiconductor layer and between the drift region and the source area. The drain area is formed in the drift region. The dielectric film is formed in the drift region and is located between the source area and the drain area. The dielectric film includes a proximate end portion and a distal end portion which are proximate to and distal from the source area, respectively, and which are asymmetrical to each other.

A power device includes: a semiconductor layer, a well region, a body region, a gate, a source, a drain, a first salicide block (SAB) layer and a second SAB layer. The first SAB layer is formed on a top surface of the semiconductor layer, and is located between the gate and the drain, wherein a part of the well is located vertically below and in contact with the first SAB layer. The second SAB layer is formed vertically above and in contact with the first SAB layer.

A power device includes: a semiconductor layer, a well region, a body region, a gate, a source, a drain, a field oxide region, and a self-aligned drift region. The field oxide region is formed on an upper surface of the semiconductor layer, wherein the field oxide region is located between the gate and the drain. The field oxide region is formed by steps including a chemical mechanical polish (CMP) process step. The self-aligned drift region is formed in the semiconductor layer, wherein the self-aligned drift region is entirely located vertically below and in contact with the field oxide region.

A semiconductor device can include: a substrate having a first doping type; a first well region located in the substrate and having a second doping type, where the first well region is located at opposite sides of a first region of the substrate; a source region and a drain region located in the first region, where the source region has the second doping type, and the drain region has the second doping type; and a buried layer having the second doping type located in the substrate and below the first region, where the buried layer is incontact with the first well region, where the first region is surrounded by the buried layer and the first well region, and the first doping type is opposite to the second doping type.

An integrated circuit has a P-type substrate and an N-type LDMOS transistor. The LDMOS transistor includes a boron-doped diffused well (DWELL-B) and an arsenic-doped diffused well (DWELL-As) located within the DWELL-B. A first polysilicon gate having first sidewall spacers and a second polysilicon gate having second sidewall spacers are located over opposite edges of the DWELL-B. A source/IBG region includes a first source region adjacent the first polysilicon gate, a second source region adjacent the second polysilicon gate, and an integrated back-gate (IBG) region located between the first and second source regions. The first source region and the second source region each include a lighter-doped source sub-region, the IBG region including an IBG sub-region having P-type dopants, and the source/IBG region includes a heavier-doped source sub-region.

Lateral double-diffused MOSFET transistor and fabrication method thereof are provided. A shallow trench isolation structure is formed in a semiconductor substrate. A drift region is formed in the semiconductor substrate and surrounding the shallow trench isolation structure. A body region is formed in the semiconductor substrate and distanced from the drift region. A gate structure is formed on a portion of each of the body region, the drift region, and the shallow trench isolation structure. A drain region is formed in the drift region on one side of the gate structure. A source region is formed in the body region on an other side of the gate structure. A first shallow doped region is formed in the drain region and the drift region to surround the shallow trench isolation structure.

Various embodiments of the present application are directed towards a method to integrate NVM devices with a logic or BCD device. In some embodiments, an isolation structure is formed in a semiconductor substrate. The isolation structure demarcates a memory region of the semiconductor substrate, and further demarcates a peripheral region of the semiconductor substrate. The peripheral region may, for example, correspond to BCD device or a logic device. A doped well is formed in the peripheral region. A dielectric seal layer is formed covering the memory and peripheral regions, and further covering the doped well. The dielectric seal layer is removed from the memory region, but not the peripheral region. A memory cell structure is formed on the memory region using a thermal oxidation process. The dielectric seal layer is removed from the peripheral region, and a peripheral device structure including a gate electrode is formed on the peripheral region.

A semiconductor device and a forming method thereof, the semiconductor device includes a first and a second wells, a source region, a drain region, two gate structures and at least one doping region. The first well with a first conductive type is disposed in a substrate, and the source region is disposed in the first well. The second well with a second conductive type is disposed adjacent to the first well in a substrate, and the drain region is disposed in the second well. Two gate structures are disposed on the substrate between the source region and the drain region. At least one doping region with the first conductive type is disposed in the second well between the two gate structures.