Provided is a doping method for doping by injecting a dopant into a processing target substrate. According to this doping method, a value of bias electric power supplied during a plasma doping processing is set to a predetermined value on premise of a washing processing to be performed after a plasma doping, and plasma is generated within a processing vessel using microwaves so as to perform the plasma doping processing on the processing target substrate hold on a holding pedestal in the processing vessel.

The present disclosure provides semiconductor structures and fabrication methods thereof. An exemplary fabrication method includes providing a plurality of fins on a semiconductor substrate; forming an anti-diffusion layer, containing anti-diffusion ions, in the fins; forming an anti-punch through layer, containing anti-punch through ions, in the fins, a top surface of the anti-punch through layer being below a top surface of the anti-diffusion layer, and the anti-diffusion layer preventing the anti-punch through ions from diffusing toward tops of the fins; and performing a thermal annealing process.

Disclosed are etchstop regions in fins of semiconductor devices, and related methods. A semiconductor device includes a buried region, a fin on the buried region, and a gate formed at least partially around the fin. At least a portion of the fin that borders the buried region includes an etchstop material. The etchstop material includes a doped semiconductor material that has a slower etch rate than that of an intrinsic form of the semiconductor material. A method of manufacturing a semiconductor device includes forming a gate on a fin, implanting part of the fin with dopants configured to decrease an etch rate of the part of the fin, removing at least part of the fin, and forming an epitaxial semiconductor material on a remaining proximal portion of the fin.

Methods of doping a semiconductor material are disclosed. Some embodiments provide for conformal doping of three dimensional structures. Some embodiments provide for doping with high concentrations of boron for p-type doping.

Non-planar semiconductor devices having doped sub-fin regions and methods of fabricating non-planar semiconductor devices having doped sub-fin regions are described. For example, a method of fabricating a semiconductor structure involves forming a plurality of semiconductor fins above a semiconductor substrate. A solid state dopant source layer is formed above the semiconductor substrate, conformal with the plurality of semiconductor fins. A dielectric layer is formed above the solid state dopant source layer. The dielectric layer and the solid state dopant source layer are recessed to approximately a same level below a top surface of the plurality of semiconductor fins, exposing protruding portions of each of the plurality of semiconductor fins above sub-fin regions of each of the plurality of semiconductor fins. The method also involves driving dopants from the solid state dopant source layer into the sub-fin regions of each of the plurality of semiconductor fins.

Techniques and mechanisms to impose stress on a transistor which includes a channel region and a source or drain region each in a fin structure. In an embodiment, a gate structure of the transistor extends over the fin structure, wherein a first spacer portion is at a sidewall of the gate structure and a second spacer portion adjoins the first spacer portion. Either or both of two features are present at or under respective bottom edges of the spacer portions. One of the features includes a line of discontinuity on the fin structure. The other feature includes a concentration of a dopant in the second spacer portion being greater than a concentration of the dopant in the source or drain region. In another embodiment, the fin structure is disposed on a buffer layer, wherein stress on the channel region is imposed at least in part with the buffer layer.

An exemplary device includes a channel layer, a first epitaxial source/drain feature, and a second epitaxial source/drain feature disposed over a substrate. The channel layer is disposed between the first epitaxial source/drain feature and the second epitaxial source/drain feature. A metal gate is disposed between the first epitaxial source/drain feature and the second epitaxial source/drain feature. The metal gate is disposed over and physically contacts at least two sides of the channel layer. A source/drain contact is disposed over the first epitaxial source/drain feature. A doped crystalline semiconductor layer, such as a gallium-doped crystalline germanium layer, is disposed between the first epitaxial source/drain feature and the source/drain contact. The doped crystalline semiconductor layer is disposed over and physically contacts at least two sides of the first epitaxial source/drain feature. In some embodiments, the doped crystalline semiconductor layer has a contact resistivity that is less than about 1×10.sup.−9 Ω-cm.sup.2.

A semiconductor device includes a FinFET fin. The same FinFET fin is associated with a bottom FinFET and a top FinFET. The FinFET fin includes a lower channel portion, associated with the bottom FinFET, a top channel portion, associated with the top FinFET, and a channel isolator between the bottom channel portion and the top channel portion. A lower gate includes a vertical portion that is upon a sidewall of the bottom channel portion. An isolation layer may be formed upon the lower gate if it is desired for the top FinFET fin and the bottom FinFET fin to not share a gate. An upper gate is upon the top channel portion and is further upon the isolation layer, if present, or is upon the lower gate.

A transistor structure is disclosed. The transistor structure includes a dielectric layer that has a thinner portion over a first doped well and a second doped well, and a thicker portion adjacent the thinner portion and over the second doped well. The thicker portion has a height greater than the thinner portion above the doped wells. The transistor includes a first gate structure on the thinner portion and a second gate structure on the thicker portion of the dielectric layer. The transistor may include a third gate structure on the thicker portion.

FinFET varactors having low threshold voltages and methods of making the same are disclosed herein. An exemplary FinFET varactor includes a fin and a gate structure disposed over a portion of the fin, such that the gate structure is disposed between a first source/drain feature and a second source/drain feature that include a first type dopant. The portion of the fin includes the first type dopant and a second type dopant. A dopant concentration of the first type dopant and a dopant concentration of the second type dopant vary from an interface between the fin and the gate structure to a first depth in the fin. The dopant concentration of the first type dopant is greater than the dopant concentration of the second type dopant from a second depth to a third depth in the fin, where the second depth and the third depth are less than the first depth.