A nitride semiconductor device includes a substrate, a first electron transport layer above the substrate, a first electron supply layer above the first electron transport layer, a first nitride semiconductor layer above the first electron supply layer, a first opening passing through the first nitride semiconductor layer and the first electron supply layer and reaching the first electron transport layer, a second electron transport layer disposed above the first nitride semiconductor layer and along the inner surface of the first opening, a second electron supply layer disposed above the second electron transport layer and covering the first opening, a gate electrode disposed above the second electron supply layer and covering the first opening, a source electrode connected to the first nitride semiconductor layer and the second electron transport layer, and a drain electrode.

A semiconductor substrate (1) includes a front surface and a back surface opposite to each other, and a through-hole (9) penetrating from the back surface to the front surface. A metal film (10) surrounding the through-hole (9) is formed in a ring shape on the front surface. A front-surface electrode (6) includes a wiring electrode (11,12) covering the through-hole (9) and the metal film (10) and is joined to the front surface outside the metal film (10). A back-surface electrode (15) is formed on the back surface and inside the through-hole (9) and connected to the wiring electrode (11,12). The metal film (10) has a lower ionization tendency and a higher work function than the wiring electrode (11,12).

A gate electrode includes a main portion formed of a gate electrode material, and a gate electrode barrier layer disposed between the main portion and a barrier layer and formed of a conductive material that prevents the gate electrode material from diffusing into the barrier layer. A surface of the main portion in a region above a first insulating layer faces a periphery without a layer of the conductive material being formed.

A semiconductor test structure includes a field-effect transistor and a metal connection structure. The field-effect transistor includes a substrate with first doping type, a gate located on a surface of the substrate, and a source region with a second doping type and a drain region with the second doping type in the substrate, the source region and the drain region are located on two sides of the gate, respectively. The metal connection structure is connected with the gate; the metal connection structure forms a Schottky contact with the substrate.

A method of manufacturing a vertical metal-semiconductor field-effect transistor (MESFET) device is provided. The method includes forming a first oxide layer, forming a first electrode in the oxide layer, forming a crystallized silicon layer on the first electrode, forming a second electrode on the first oxide layer and on sidewalls of the crystalized silicon layer, forming a second oxide layer on upper surfaces of the second electrode. The method also includes forming a third electrode on an upper surface of the crystallized silicon layer.

FETs used in a conventional current-to-voltage converter lack current-to-voltage conversion efficiency when operated at cryogenic temperatures, and it is difficult to sensitively measure current. A desired low-temperature environment cannot be realized either due to the heat inflow into a cooling device from outside. A current-to-voltage converter is provided that sensitively measures small currents even in extremely low-temperature conditions. The current-to-voltage converter of the present disclosure uses elements exclusively optimized for low-temperature operation (e.g., HEMTs) as electronic elements for current-to-voltage conversion. Significantly more excellent current-to-voltage conversion characteristics than those of the conventional technique are realized even when the current-to-voltage converter is operated at a low temperature of 150K or less or in cryogenic temperature conditions close to absolute zero. Power supply to the current-to-voltage conversion circuit and a bias circuit are simplified, and the heat inflow into the cooling device from outside is suppressed, thus reducing the load on the cooling device.

A semiconductor device including: a first silicon layer including a first single crystal silicon and a plurality of first transistors; a first metal layer disposed over the first silicon layer; a second metal layer disposed over the first metal layer; a third metal layer disposed over the second metal layer; a second level including a plurality of second transistors, the second level disposed over the third metal layer; a fourth metal layer disposed over the second level; a fifth metal layer disposed over the fourth metal layer, where the fourth metal layer is aligned to first metal layer with a less than 40 nm alignment error; and a via disposed through the second level, where each of the second transistors includes a metal gate, and where a typical thickness of the second metal layer is greater than a typical thickness of the third metal layer by at least 50%.

A 3D integrated circuit, the circuit including: a first level including a first wafer, the first wafer including a first crystalline substrate, a plurality of first transistors, and first copper interconnecting layers, where the first copper interconnecting layers at least interconnect the plurality of first transistors; and a second level including a second wafer, the second wafer including a second crystalline substrate, a plurality of second transistors, and second copper interconnecting layers, where the second copper interconnecting layers at least interconnect the plurality of second transistors, where the second level is bonded to the first level, where the bonded includes metal to metal bonding, where the bonded includes oxide to oxide bonding, and where at least one of the second transistors include a replacement gate.

A semiconductor device including: a first silicon level including a first single crystal silicon layer and a plurality of first transistors; a first metal layer disposed over the first silicon level; a second metal layer disposed over the first metal layer; a third metal layer disposed over the second metal layer; a second level including a plurality of second transistors, the second level disposed over the third metal layer; a fourth metal layer disposed over the second level; a fifth metal layer disposed over the fourth metal layer, where the fourth metal layer is aligned to the first metal layer with a less than 40 nm alignment error; a via disposed through the second level, where each of the second transistors includes a metal gate, where a typical thickness of the second metal layer is greater than a typical thickness of the third metal layer by at least 50%.

A composite substrate of the present disclosure is composed of two parts: a SiC substrate; and a Si-containing thermal-sprayed layer made of a material obtained by melting Si or a Si alloy through thermal spraying. The Si-containing thermal-sprayed layer serves as a support substrate for supporting the SiC substrate so as to keep the mechanical strength thereof, and is provided at one surface of the SiC substrate on the side opposite to a surface where a nitride semiconductor layer composed of layers made of nitride semiconductors such as an AlN buffer layer, a GaN buffer layer, and an AlGaN Schottky layer is formed through epitaxial growth.