A tunneling transistor includes a gate, an insulating layer placed on the gate, a carbon nanotube being semiconducting, a film-like structure, a source electrode, and a drain electrode. The carbon nanotube is placed on a surface of the insulating layer away from the gate. The film-like structure covers a portion of the carbon nanotube, and the film-like structure is a molybdenum disulfide film or a tungsten disulfide film. The source electrode is electrically connected to the film-like structure. The drain electrode is electrically connected to the carbon nanotube.

An apparatus comprising: a fermion source nanolayer (90); a first insulating nanolayer (92); a fermion transport nanolayer (94); a second insulating nanolayer (96); a fermion sink nanolayer (98); a first contact for applying a first voltage to the fermion source nanolayer; a second contact for applying a second voltage to the fermion sink nanolayer; and a transport contact for enabling an electric current via the fermion transport nanolayer. In a particular example, the apparatus comprises three graphene sheets (90, 94, 98) interleaved with two-dimensional Boron-Nitride (hBN) layers (92, 96).

The current disclosure describes a new vertical tunnel field-effect transistor (TFET). The TFET includes a source layer over a substrate. A first channel layer is formed over the source layer. A drain layer is stacked over the first channel layer with a second channel layer stacked therebetween. The drain layer and the second channel layer overlap a first surface portion of the first channel layer. A gate structure is positioned over the channel layer by a second surface portion of the channel layer and contacts a sidewall of the second channel layer.

A TEFT includes a drain region on a substrate, a channel on the drain region, a dipole formation layer (DFL) on the channel, a dipole formation layer (DFL) on the channel, a source region on the DFL, a gate insulation pattern surrounding the channel, and a gate electrode surrounding the gate insulation pattern. The DFL contacts the channel and the source region and form dipoles between the channel and the source region.

The current disclosure describes a new vertical tunnel field-effect transistor (TFET). The TFET includes a source layer over a substrate. A first channel layer is formed over the source layer. A drain layer is stacked over the first channel layer with a second channel layer stacked therebetween. The drain layer and the second channel layer overlap a first surface portion of the first channel layer. A gate structure is positioned over the channel layer by a second surface portion of the channel layer and contacts a sidewall of the second channel layer.

Described herein are various amorphous metal thin film transistors. Embodiments of such transistors include an amorphous metal gate electrode and a channel conductor formed on a non-conducting substrate. Further embodiments of such transistors include an amorphous metal source electrode, an amorphous metal drain electrode, and a channel conductor formed on a non-conducting substrate. Methods of forming such transistors are also described.

Provided are P-type semiconductor layer, P-type multilevel element, and manufacturing method for the element. The P-type multilevel element comprises a gate electrode, an active structure overlapping the gate electrode, a gate insulating layer disposed between the gate electrode and the active structure, and source and drain electrodes electrically connected to both ends of the active structure, respectively. The active structure has a first P-type active layer, a second P-type active layer, and a barrier layer disposed between the first P-type active layer and the second P-type active layer. A threshold voltage for forming a channel in the first P-type active layer and a threshold voltage for forming a channel in the second P-type active layer have different values.

Described herein are various amorphous metal thin film transistors. Embodiments of such transistors include an amorphous metal gate electrode and a channel conductor formed on a non-conducting substrate. Further embodiments of such transistors include an amorphous metal source electrode, an amorphous metal drain electrode, and a channel conductor formed on a non-conducting substrate. Methods of forming such transistors are also described.

Double gated thin film transistors are described. In an example, an integrated circuit structure includes an insulator layer above a substrate. A first gate electrode is on the insulator layer, the first gate electrode having a non-planar feature. A first gate dielectric is on and conformal with the non-planar feature of the first gate electrode. A channel material layer is on and conformal with the first gate dielectric. A second gate dielectric is on and conformal with the channel material layer. A second gate electrode is on and conformal with the second gate dielectric. A first source or drain region is coupled to the channel material layer at a first side of the first gate dielectric. A second source or drain region is coupled to the channel material layer at a second side of the first gate dielectric.

The disclosure describes a tunneling field effect transistor having an overlapping structure between the source and drain regions providing a greater tunneling area. The source or drain region may be a doped region in a semi-conductive substrate. The other source or drain region may be formed by epitaxial deposition over the doped region. The gate is formed over the epitaxial region where the doped and epitaxial regions overlap. The doped region may be formed in a fin structure with the epitaxial region and gate being formed on the top and sides of the fin.