Memory systems and devices with source plate discharge circuits (and associated methods) are described herein. In one embodiment, a memory device includes (a) a plurality of memory cells, (b) a source plate electrically coupled to the plurality of memory cells, and (c) a discharge circuit. The discharge circuit can include a bipolar junction transistor device electrically coupled to the source plate and configured to drop a voltage at the source plate by, for example, discharging current through the bipolar junction transistor device. In some embodiments, the bipolar junction transistor device can be activated using a low-voltage switch or a high-voltage switch electrically coupled to the bipolar junction transistor. In these and other embodiments, the bipolar junction transistor device can operate in an avalanche mode while discharging current to drop the voltage at the source plate.

Memory systems and devices with source plate discharge circuits (and associated methods) are described herein. In one embodiment, a memory device includes (a) a plurality of memory cells, (b) a source plate electrically coupled to the plurality of memory cells, and (c) a discharge circuit. The discharge circuit can include a bipolar junction transistor device electrically coupled to the source plate and configured to drop a voltage at the source plate by, for example, discharging current through the bipolar junction transistor device. In some embodiments, the bipolar junction transistor device can be activated using a low-voltage switch or a high-voltage switch electrically coupled to the bipolar junction transistor. In these and other embodiments, the bipolar junction transistor device can operate in an avalanche mode while discharging current to drop the voltage at the source plate.

The present technique relates to an electrostatic protective element that enables protective performance with respect to static electricity to be improved and to an electronic device. An electrostatic protective element includes: a first impurity region of a first conductivity type which is formed on the predetermined surface side of a semiconductor substrate; a second impurity region of a second conductivity type which is formed on the predetermined surface side of the semiconductor substrate so as to form a clearance in a horizontal direction with respect to the first impurity region; a collector contact which is formed on the predetermined surface side in the first impurity region, which has a higher concentration than the first impurity region, and which is an impurity region of the first conductivity type; a base contact which is formed on the predetermined surface side in the second impurity region, which has a higher concentration than the second impurity region, and which is an impurity region of the second conductivity type; and an emitter contact which is formed on the predetermined surface side in the second impurity region at a position that is closer to the collector contact than the base contact, which has a higher concentration than the second impurity region, and which is an impurity region of the first conductivity type. The present technique can be applied to, for example, an electronic device.

The present technique relates to an electrostatic protective element that enables protective performance with respect to static electricity to be improved and to an electronic device. An electrostatic protective element includes: a first impurity region of a first conductivity type which is formed on the predetermined surface side of a semiconductor substrate; a second impurity region of a second conductivity type which is formed on the predetermined surface side of the semiconductor substrate so as to form a clearance in a horizontal direction with respect to the first impurity region; a collector contact which is formed on the predetermined surface side in the first impurity region, which has a higher concentration than the first impurity region, and which is an impurity region of the first conductivity type; a base contact which is formed on the predetermined surface side in the second impurity region, which has a higher concentration than the second impurity region, and which is an impurity region of the second conductivity type; and an emitter contact which is formed on the predetermined surface side in the second impurity region at a position that is closer to the collector contact than the base contact, which has a higher concentration than the second impurity region, and which is an impurity region of the first conductivity type. The present technique can be applied to, for example, an electronic device.

A semiconductor device includes a first semiconductor well. The semiconductor device includes a channel structure disposed above the first semiconductor well and extending along a first lateral direction. The semiconductor device includes a gate structure extending along a second lateral direction and straddling the channel structure. The semiconductor device includes a first epitaxial structure disposed on a first side of the channel structure. The semiconductor device includes a second epitaxial structure disposed on a second side of the channel structure, the first side and second side opposite to each other in the first lateral direction. The first epitaxial structure is electrically coupled to the first semiconductor well with a second semiconductor well in the first semiconductor well, and the second epitaxial structure is electrically isolated from the first semiconductor well with a dielectric layer.

A semiconductor device includes a first semiconductor well. The semiconductor device includes a channel structure disposed above the first semiconductor well and extending along a first lateral direction. The semiconductor device includes a gate structure extending along a second lateral direction and straddling the channel structure. The semiconductor device includes a first epitaxial structure disposed on a first side of the channel structure. The semiconductor device includes a second epitaxial structure disposed on a second side of the channel structure, the first side and second side opposite to each other in the first lateral direction. The first epitaxial structure is electrically coupled to the first semiconductor well with a second semiconductor well in the first semiconductor well, and the second epitaxial structure is electrically isolated from the first semiconductor well with a dielectric layer.

A semiconductor device includes: a drift region of a first conductive type including a contact section and extension sections extending along the main surface of a substrate; column regions of a second conductive type which alternate with the extension sections in a perpendicular direction to the extension direction of the extension sections and each includes an end connecting to the contact section; a well region of a second conductive type which connects to the other end of each column region and tips of the extension sections; and electric field relaxing electrodes which are provided above at least some of residual pn junctions with an insulating film interposed therebetween. Herein, the residual pn junctions are pn junctions other than voltage holding pn junctions formed in interfaces between the extension sections and the column regions.

A lateral insulated gate bipolar transistor, comprising: a substrate (100), having a first conductivity type; an insulating layer (200), formed on the substrate (100); an epitaxial layer (300), having a second conductivity type and formed on the insulating layer (200); a field oxide layer (400), formed on the epitaxial layer (300); a first well (500), having the first conductivity type; a plurality of gate trench structures (600); second source doped regions (720), having the second conductivity type; first source doped regions (710), having the first conductivity type; a second well (800), having the second conductivity type; a first drain doped region (910), having the first conductivity type and formed on a surface layer of the second well (800); gate lead-out ends (10); a source lead-out end (20); a drain lead-out end (30).

Structures for a bipolar junction transistor and methods of forming a structure for a bipolar junction transistor. The structure includes an emitter having a raised portion, a collector having a raised portion, and a base having a base layer and an extrinsic base layer stacked with the base layer. The base layer and the extrinsic base layer are positioned in a lateral direction between the raised portion of the emitter and the raised portion of the collector, the base layer has a first width in the lateral direction, the extrinsic base layer has a second width in the lateral direction, and the second width is greater than the first width.

Structures for a bipolar junction transistor and methods of forming a structure for a bipolar junction transistor. The structure includes an emitter having a raised portion, a collector having a raised portion, and a base having a base layer and an extrinsic base layer stacked with the base layer. The base layer and the extrinsic base layer are positioned in a lateral direction between the raised portion of the emitter and the raised portion of the collector, the base layer has a first width in the lateral direction, the extrinsic base layer has a second width in the lateral direction, and the second width is greater than the first width.