Patent classifications
H01L29/7376
Germanium-Silicon-Tin (GeSiSn) Heterojunction Bipolar Transistor Devices
A semiconductor device having a GeSiSn base region combined with an emitter region and a collector region can be used to fabricate a bipolar transistor or a heterojunction bipolar transistor. The GeSiSn base region can be compositionally graded or latticed matched or strained to GaAs. The GeSiSn base region can be wafer bonded to a GaN or SiC collector region.
Germanium-silicon-tin (GeSiSn) heterojunction bipolar transistor devices
The methods of manufacture of GeSiSn heterojunction bipolar transistors, which include light emitting transistors and transistor lasers and photo-transistors and their related structures are described herein. Other embodiments are also disclosed herein.
Two-channel semiconductor component
A two-channel semiconductor component has a doped semiconductor body formed from a group IV semiconductor material, a top-side top-gate electrode, and a bottom-side bottom-gate electrode. A source region has a greater extent in a depth direction in the silicon body than a drain region. A source isolation region is arranged between a source region and the top-gate electrode, and a drain isolation region is arranged between a drain region and the top-gate electrode, which isolation region extends in a depth direction as far as to the lower edge of a gate isolation layer of the top-gate electrode. In a first operating state a first conductive channel separated laterally from the source region by the source isolation region can be formed, as can a second conductive channel, which is decoupled from the first conductive channel by a barrier region of the semiconductor body extending in a depth direction between the conductive channels. In a second operating state which satisfies a resonance condition, the first and second conductive channel can be coupled to one another by means of a tunnel effect for minority charge carriers over the barrier region of the semiconductor body.
TWO-CHANNEL SEMICONDUCTOR COMPONENT
A two-channel semiconductor component has a doped semiconductor body formed from a group IV semiconductor material, a top-side top-gate electrode, and a bottom-side bottom-gate electrode. A source region has a greater extent in a depth direction in the silicon body than a drain region. A source isolation region is arranged between a source region and the top-gate electrode, and a drain isolation region is arranged between a drain region and the top-gate electrode, which isolation region extends in a depth direction as far as to the lower edge of a gate isolation layer of the top-gate electrode. In a first operating state a first conductive channel separated laterally from the source region by the source isolation region can be formed, as can a second conductive channel, which is decoupled from the first conductive channel by a barrier region of the semiconductor body extending in a depth direction between the conductive channels. In a second operating state which satisfies a resonance condition, the first and second conductive channel can be coupled to one another by means of a tunnel effect for minority charge carriers over the barrier region of the semiconductor body.
Semiconductor device including resonant tunneling diode structure having a superlattice
A semiconductor device may include at least one double-barrier resonant tunneling diode (DBRTD). The at least one DBRTD may include a first doped semiconductor layer and a first barrier layer on the first doped semiconductor layer and including a superlattice. The superlattice may include stacked groups of layers, each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The at least one DBRTD may further include an intrinsic semiconductor layer on the first barrier layer, a second barrier layer on the intrinsic semiconductor layer, and a second doped semiconductor layer on the second superlattice layer.
Method of Manufacture of Germanium-Silicon-Tin Heterojunction Bipolar Transistor Devices
The methods of manufacture of GeSiSn heterojunction bipolar transistors, which include light emitting transistors and transistor lasers and photo-transistors and their related structures are described herein. Other embodiments are also disclosed herein.
Method for making a semiconductor device including a resonant tunneling diode structure having a superlattice
A method for making a semiconductor device may include forming at least one double-barrier resonant tunneling diode (DBRTD) by forming a first doped semiconductor layer, and forming a first barrier layer on the first doped semiconductor layer and including a superlattice. The superlattice may include stacked groups of layers, each group of layers including stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming an intrinsic semiconductor layer on the first barrier layer, forming a second barrier layer on the intrinsic semiconductor layer, and forming a second doped semiconductor layer on the second superlattice layer.
Semiconductor device including a resonant tunneling diode structure with electron mean free path control layers
A semiconductor device including at least one double-barrier resonant tunneling diode (DBRTD) is provided. The at least one DBRTD may include a first doped semiconductor layer, and a first barrier layer on the first doped semiconductor layer and including a superlattice. The DBRTD may further include a first intrinsic semiconductor layer on the first barrier layer, a second barrier layer on the first intrinsic semiconductor layer and also including the superlattice, a second intrinsic semiconductor layer on the second barrier layer, a third barrier layer on the second intrinsic semiconductor layer and also including the superlattice. A third intrinsic semiconductor layer may be on the third barrier layer, a fourth barrier layer may be on the third intrinsic semiconductor layer and also including the superlattice, a second doped semiconductor layer on the fourth barrier layer.
Method for making a semiconductor device including a resonant tunneling diode with electron mean free path control layers
A method for making a semiconductor device may include forming at least one a double-barrier resonant tunneling diode (DBRTD) by forming a first doped semiconductor layer, and a forming first barrier layer on the first doped semiconductor layer and including a superlattice. The method may further include forming a first intrinsic semiconductor layer on the first barrier layer, forming a second barrier layer on the first intrinsic semiconductor layer and also comprising the superlattice, forming a second intrinsic semiconductor layer on the second barrier layer, and forming a third barrier layer on the second intrinsic semiconductor layer and also comprising the superlattice. The method may further include forming a third intrinsic semiconductor layer on the third barrier layer, forming a fourth barrier layer on the third intrinsic semiconductor layer, and forming a second doped semiconductor layer on the fourth barrier layer.
METHOD FOR MAKING A SEMICONDUCTOR DEVICE INCLUDING A RESONANT TUNNELING DIODE WITH ELECTRON MEAN FREE PATH CONTROL LAYERS
A method for making a semiconductor device may include forming at least one a double-barrier resonant tunneling diode (DBRTD) by forming a first doped semiconductor layer, and a forming first barrier layer on the first doped semiconductor layer and including a superlattice. The method may further include forming a first intrinsic semiconductor layer on the first barrier layer, forming a second barrier layer on the first intrinsic semiconductor layer and also comprising the superlattice, forming a second intrinsic semiconductor layer on the second barrier layer, and forming a third barrier layer on the second intrinsic semiconductor layer and also comprising the superlattice. The method may further include forming a third intrinsic semiconductor layer on the third barrier layer, forming a fourth barrier layer on the third intrinsic semiconductor layer, and forming a second doped semiconductor layer on the fourth barrier layer.