A semiconductor arrangement and method of manufacture is provided. In some embodiments, a semiconductor arrangement includes a collector region having a first surface coplanar with a first surface of a semiconductor layer, a drift region over a portion of the collector region and having a first surface coplanar with the first surface of the semiconductor layer, and a body region over the drift region. A body contact is in the body region. An emitter contact contacts the body contact and the body region. A collector contact contacts the first surface of the collector region. A first gate structure is adjacent the first surface of the drift region, the body region, and the body contact.

To provide a highly reliable semiconductor device having both an improved breakdown voltage and a reduced withstand voltage leakage current. An intermediate resistive field plate is comprised of a first intermediate resistive field plate coupled, at one end thereof, to an inner-circumferential-side resistive field plate and, at the other end, to an outer-circumferential-side resistive field plate and a plurality of second intermediate resistive field plates. The first intermediate resistive field plate has a planar pattern that is equipped with a plurality of first portions separated from each other in a first direction connecting the inner-circumferential resistive field plate to the outer-circumferential-side resistive field plate and linearly extending in a second direction orthogonal to the first direction, and repeats reciprocation along the second direction. The second intermediate resistive field plates are each connected with a first end portion on one side of the first portions and extend with a curvature.

Disclosed are a semiconductor device, a preparation method therefor and electrical equipment thereof. The semiconductor device includes: a silicon substrate on which an emitter, a gate, and a collector are formed; a bootstrap electrode formed on the silicon substrate; and an insulating layer, formed on the silicon substrate and disposed between the emitter and the bootstrap electrode. A bootstrap capacitor is formed between the emitter and the bootstrap electrode.

Provided is a semiconductor device including a gate trench portion and a first trench portion adjacent to the gate trench portion. The device may include a first conductivity type drift region provided in a semiconductor substrate, a second conductivity type base region provided above the drift region, a first conductivity type emitter region provided above the base region and having a doping concentration higher than that of the drift region, and a second conductivity type contact region provided above the base region and having a doping concentration higher than that of the base region. The contact region includes a first contact portion provided on a front surface of the substrate, and a second contact portion having a doping concentration different from that of the first contact portion and provided alternately with the first contact portion in a trench extending direction on a side wall of the first trench portion.

The present disclosure relates to an insulated gate bipolar transistor and a method of manufacturing the same. More particularly, the present disclosure relates to an insulated gate bipolar transistor and a manufacturing method that improves breakdown voltage characteristics and includes a second ring region having a first conductivity type in contact with a first ring region having the first conductivity type in the termination region.

A semiconductor device includes: a semiconductor layer of a first conductivity type having a first main surface and a second main surface; an active region defined in a surface layer of the first main surface; an outer region defined outside the active region in the surface layer; and a main junction region of a second conductivity type provided in the outer region as surrounding the active region. The semiconductor device includes: a floating region of the second conductivity type provided in an electrically floating state in the active region; a region isolation trench structure which isolates the floating region in the surface layer; an outer isolation trench structure disposed in spaced relation from the region isolation trench structure to define the main junction region outward thereof; and an intervening region disposed between the region isolation trench structure and the outer isolation trench structure.

An emitter interconnection connecting the emitter of a semiconductor switching element to a negative electrode is different in one or both of length and width from an emitter interconnection connecting the emitter of a semiconductor switching element to the negative electrode. At the time of switching, an induced electromotive force is generated at a gate control wire, or at a gate pattern, or at an emitter wire, by at least one of a current flowing through a positive electrode and a current flowing through the negative electrode, so as to reduce the difference between the emitter potential of the semiconductor switching element and the emitter potential of the semiconductor switching element caused by the difference.

An insulated gate bipolar transistor includes a substrate; a first conductivity type base disposed on the substrate and having a first trench; a first conductivity type buffer region disposed in the first conductivity type base; a collector doped region having a second conductivity type and disposed in the first conductivity type base; a second conductivity type base to which the first trench extends downwardly; a gate oxide layer disposed on an inner surface of the first trench; a polysilicon gate disposed inside the gate oxide layer; an emitter doped region having a first conductivity type and disposed in the second conductivity type base and under the first trench; a conductive plug extending downwardly from above the first trench and contacting the second conductivity type base; and an insulating oxide layer filled in the first trench, the insulating oxide layer insulating and isolating the polysilicon gate from the emitter doped region.

A chip includes a semiconductor body coupled to a first and a second load terminal. The semiconductor body includes an active region including a plurality of breakthrough cells, each of the breakthrough cells includes: an insulation structure; a drift region; an anode region, the anode region being electrically connected to the first load terminal and disposed in contact with the first load terminal; a first barrier region arranged in contact with each of the anode region and the insulation structure, where the first barrier region of the plurality of breakthrough cells forms a contiguous semiconductor layer; a second barrier region separating each of the anode region and at least a part of the first barrier region from the drift region; and a doped contact region arranged in contact with the second load terminal, where the drift region is positioned between the second barrier region and the doped contact region.

A method of forming an IC including a power semiconductor device includes providing a substrate having an epi layer thereon with at least one transistor formed therein covered by a pre-metal dielectric (PMD) layer. Contact openings are etched from through the PMD into the epi layer to form a sinker trench extending to a first node of the device. A metal fill material is deposited to cover a sidewall and bottom of the sinker trench but not completely fill the sinker trench. A dielectric filler layer is deposited over the metal fill material to fill the sinker trench. An overburden region of the dielectric filler layer is removed stopping on a surface of the metal fill material in the overburden region to form a sinker contact. A patterned interconnect metal is formed providing a connection between the interconnect metal and metal fill material on the sidewall of the sinker trench.