A gate-turn-off thyristor is provided. The gate-turn-off thyristor includes a plurality of strips formed by repeatedly arranging a plurality of N-type emitter regions with high doping concentration of an upper transistor on an upper surface of an N-type silicon substrate with high resistivity, wherein a periphery of each strip of the plurality of strips is surrounded with a P-type dense base region bus bar of the upper transistor, a cathode metal layer is disposed on an N-type emitter region of the plurality of N-type emitter regions of the upper transistor, and a P-type base region of the upper transistor is disposed below the N-type emitter region of the upper transistor; a side of the P-type base region of the upper transistor is connected to a P-type dense base region of the upper transistor or a P-type dense base region bus bar of the upper transistor.

An integrated gate-commutated thyristor (IGCT) includes a semiconductor wafer having a first main side and a second main side opposite to the first main side and a plurality of first type thyristor cells and second type thyristor cells. The cathode electrode of the first type thyristor cells forms an ohmic contact with the cathode region and the cathode electrode of the second type thyristor cells is insulated from the cathode region. A predefined percentage of second type thyristor cells of the overall amount of first type thyristor cells and second type thyristor cells in a segment ring is greater than .sub.0% and less than or equal to 75%.

A turn-off power semiconductor device includes first and second thyristor cells, a common gate contact and a plurality of stripe-shaped electrically conductive first gate runners. Each first gate runner has a first end portion, a second end portion opposite to the first end portion and a first connecting portion connecting the first end portion and the second end portion. The first end portion is directly connected to the common gate contact. The first gate electrode layer portions of all first thyristor cells are implemented as a first gate electrode layer. The second gate electrode layer portions of all second thyristor cells are implemented as a second gate electrode layer. The first gate electrode layer is directly connected to the common gate contact. At least the first connecting portion of each first gate runner is separated from the first gate electrode layer.

The SCR-based ESD device has a 4-layered PNPN structure (NPN and PNP junction transistors) disposed in SOI having first and second device wells (N-well and P-well) abut forming a NP junction near a midline. First and second contact regions disposed in device wells are coupled to high and low power sources (I/O pad and ground). Internal isolation regions (shallower STI) extending partially not touching the bottom of surface substrate separate the first and second contact regions. A vertical gate is disposed over the NP junction or over a shallower STI which overlaps the NP junction and separate the second contact regions in x-direction. One or more horizontal gates separate the second contact regions in y-direction and guide the device wells underneath the shallower STI to outer edges to connect with the first contact regions for body contacts. A process for forming the device is also disclosed and is compatible with CMOS processes.

The SCR-based ESD device has a 4-layered PNPN structure (NPN and PNP junction transistors) disposed in SOI having first and second device wells (N-well and P-well) abut forming a NP junction near a midline. First and second contact regions disposed in device wells are coupled to high and low power sources (I/O pad and ground). Internal isolation regions (shallower STI) extending partially not touching the bottom of surface substrate separate the first and second contact regions. A vertical gate is disposed over the NP junction or over a shallower STI which overlaps the NP junction and separate the second contact regions in x-direction. One or more horizontal gates separate the second contact regions in y-direction and guide the device wells underneath the shallower STI to outer edges to connect with the first contact regions for body contacts. A process for forming the device is also disclosed and is compatible with CMOS processes.

This electrostatic protection circuit enables a high hold voltage to be set, and acts to accurately prevent breakdown of a protected circuit immediately after power on, and to prevent breakdown or deterioration of a protection device during prolonged normal operation, without connecting a resistance element in parallel to a plurality of circuit blocks connected in series. This electrostatic protection circuit is provided with a plurality of circuit blocks connected in series between a first node and a second node, at least one circuit block out of the plurality of circuit blocks including a thyristor having an anode connected to one end of the at least one circuit block and a cathode connected to the other end of the at least one circuit block. When the potential of the first node is higher than the potential of the second node during normal operation, the voltage between both ends of the other circuit blocks out of the plurality of circuit blocks is smaller than the voltage between the anode and the cathode of the thyristor.

This electrostatic protection circuit enables a high hold voltage to be set, and acts to accurately prevent breakdown of a protected circuit immediately after power on, and to prevent breakdown or deterioration of a protection device during prolonged normal operation, without connecting a resistance element in parallel to a plurality of circuit blocks connected in series. This electrostatic protection circuit is provided with a plurality of circuit blocks connected in series between a first node and a second node, at least one circuit block out of the plurality of circuit blocks including a thyristor having an anode connected to one end of the at least one circuit block and a cathode connected to the other end of the at least one circuit block. When the potential of the first node is higher than the potential of the second node during normal operation, the voltage between both ends of the other circuit blocks out of the plurality of circuit blocks is smaller than the voltage between the anode and the cathode of the thyristor.

An ion implantation apparatus includes an ion beam directing unit, a substrate support, and a controller. The controller is configured to effect a relative movement between an ion beam passing the ion beam directing unit and the substrate support. A beam track of the ion beam on a substrate mounted on the substrate support includes circles or a spiral.

An ion implantation apparatus includes an ion beam directing unit, a substrate support, and a controller. The controller is configured to effect a relative movement between an ion beam passing the ion beam directing unit and the substrate support. A beam track of the ion beam on a substrate mounted on the substrate support includes circles or a spiral.

An insulated gate turn-off thyristor has a layered structure including a p+ layer (e.g., a substrate), an n-epi layer, a p-well, vertical insulated gate regions formed in the p-well, and an p-layer over the p-well and between the gate regions, so that vertical npn and pnp transistors are formed. The p-well has an intermediate highly doped portion. When the gate regions are sufficiently biased, an inversion layer surrounds the gate regions, causing the effective base of the npn transistor to be narrowed to increase its beta. When the product of the betas exceeds one, controlled latch-up of the thyristor is initiated. The p-well's highly doped intermediate region enables improvement in the npn transistor efficiency as well as enabling more independent control over the characteristics of the n-type layer (emitter), the emitter-base junction characteristics, and the overall dopant concentration and thickness of the p-type base.