Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; a plurality of gates disposed on the quantum well stack; and a top gate at least partially disposed on the plurality of gates such that the plurality of gates are at least partially disposed between the top gate and the quantum well stack.

A quantum dot device is disclosed that includes a quantum well stack, a first and a second plunger gates above the quantum well stack, and a passive barrier element provided in a portion of the quantum well stack between the first and the second plunger gates. The passive barrier element may serve as means for localizing charge in the quantum dot device and may be used to replace charge localization control by means of a barrier gate. In general, a quantum dot device with a plurality of plunger gates provided over a given quantum well stack may include a respective passive barrier element between any, or all, of adjacent plunger gates in the manner as described for the first and second plunger gates.

Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum processing device may include a quantum well stack, the quantum well stack includes a quantum well layer, the quantum processing device further includes a plurality of gates above the quantum well stack to control quantum dot formation in the quantum well stack, and (1) gate metal of individual gates of the array of gates is tapered so as to narrow farther from the quantum well stack or (2) top surfaces of gate metal of individual gates of the array of gates are dished.

A bidirectional switch element includes: a substrate; an Al.sub.zGa.sub.1-zN layer; an Al.sub.bGa.sub.1-bN layer; a first source electrode; a first gate electrode; a second gate electrode; a second source electrode; a p-type Al.sub.x1Ga.sub.1-x1N layer; a p-type Al.sub.x2Ga.sub.1-x2N layer; an Al.sub.yGa.sub.1-yN layer; and an Al.sub.wGa.sub.1-wN layer. The Al.sub.zGa.sub.1-zN layer is formed over the substrate. The Al.sub.bGa.sub.1-bN layer is formed on the Al.sub.zGa.sub.1-zN layer. The Al.sub.yGa.sub.1-yN layer is interposed between the substrate and the Al.sub.zGa.sub.1-zN layer. The Al.sub.wGa.sub.1-wN layer is interposed between the substrate and the Al.sub.yGa.sub.1-yN layer and has a higher C concentration than the Al.sub.yGa.sub.1-yN layer.

A semiconductor structure includes: a channel layer; an active layer over the channel layer, wherein the active layer is configured to form a two-dimensional electron gas (2DEG) to be formed in the channel layer along an interface between the channel layer and the active layer; a gate electrode over a top surface of the active layer; and a source/drain electrode over the top surface of the active layer; wherein the active layer includes a first layer and a second layer sequentially disposed therein from the top surface to a bottom surface of the active layer, and the first layer possesses a higher aluminum (Al) atom concentration compared to the second layer. An HEMT structure and an associated method are also disclosed.

Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; an insulating material disposed above the quantum well stack, wherein the insulating material includes a trench; and a gate metal disposed on the insulating material and extending into the trench.

Semiconductor element, method of reading out a quantum dot device and system. The present document relates to a semiconductor element for providing a source reservoir for a charge sensor of a quantum dot device. The element comprises a semiconductor heterostructure (2, 3, 5) including a quantum well layer (5) contiguous to a semiconductor functional layer (3), one or more ohmic contacts (9) for providing charge carriers, and a first accumulation gate electrode (13) located opposite the quantum well layer and spaced apart therefrom at least by the semiconductor functional layer for enabling to form a two dimensional charge carrier gas (14) in a first area of the quantum well layer upon applying a first biasing voltage to the first accumulation gate electrode. The device further comprises a second accumulation gate electrode (17) opposite the quantum well layer and electrically isolated from the first accumulation gate electrode (13), the second accumulation gate electrode enabling to be biased with a second biasing voltage, for enabling to extend the two dimensional charge carrier gas in a second area (18) contiguous to the first area. This document further relates to a method of determining a spin state in a quantum dot device, as well as a system comprising a quantum dot device and a semiconductor element.

The present disclosure describes a method that includes forming a first two-dimensional (2D) layer on a first substrate and attaching a second 2D layer to a carrier film. The method also includes bonding the second 2D layer to the first 2D layer to form a heterostack including the first and second 2D layers. The method further includes separating the first 2D layer of the heterostack from the first substrate and attaching the heterostack to a second substrate. The method further includes removing the carrier film from the second 2D layer.

A quantum semiconductor device is provided. The quantum semiconductor device includes a quantum heterostructure, a dielectric layer, and an electrode. The quantum heterostructure includes a quantum well layer that includes a first 2DEG region, a second 2DEG region, and a third 2DEG region. A first tunnel barrier exists between the first 2DEG region and the second 2DEG region. A second tunnel barrier exists between the second 2DEG region and the third 2DEG region. A third tunnel barrier exists either between the first 2DEG region and the third 2DEG region. The dielectric layer is formed on the quantum heterostructure. The electrode is formed on the dielectric layer directly above the first tunnel barrier.

A sputtering target including an oxide with a low impurity concentration is provided. Provided is a method for manufacturing a sputtering target, including a first step of preparing a mixture including indium, zinc, an element M (the element M is aluminum, gallium, yttrium, or tin), and oxygen; a second step of raising a temperature of the mixture from a first temperature to a second temperature in a first atmosphere containing nitrogen at a concentration of higher than or equal to 90 vol % and lower than or equal to 100 vol %; and a third step of lowering the temperature of the mixture from the second temperature to a third temperature in a second atmosphere containing oxygen at a concentration of higher than or equal to 10 vol % and lower than or equal to 100 vol %.