Techniques and methods related to strained NMOS and PMOS devices without relaxed substrates, systems incorporating such semiconductor devices, and methods therefor may include a semiconductor device that may have both n-type and p-type semiconductor bodies. Both types of semiconductor bodies may be formed from an initially strained semiconductor material such as silicon germanium. A silicon cladding layer may then be provided at least over or on the n-type semiconductor body. In one example, a lower portion of the semiconductor bodies is formed by a Si extension of the wafer or substrate. By one approach, an upper portion of the semiconductor bodies, formed of the strained SiGe, may be formed by blanket depositing the strained SiGe layer on the Si wafer, and then etching through the SiGe layer and into the Si wafer to form the semiconductor bodies or fins with the lower and upper portions.

Disclosed herein are quantum dot devices and techniques. In some embodiments, a quantum computing processing device may include a quantum well stack, an array of quantum dot gate electrodes above the quantum well stack, and an associated array of selectors above the array of quantum dot gate electrodes. The array of quantum dot gate electrodes and the array of selectors may each be arranged in a grid.

Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a substrate and a quantum well stack disposed on the substrate. The quantum well stack may include a quantum well layer and a back gate, and the back gate may be disposed between the quantum well layer and the substrate.

An N-polar III-N high-electron mobility transistor device can include a III-N channel layer over an N-face of a III-N backbarrier, wherein a compositional difference between the channel layer and the backbarrier causes a 2DEG channel to be induced in the III-N channel layer adjacent to the interface between the III-N channel layer and the backbarrier. The device can further include a p-type III-N layer over the III-N channel layer and a thick III-N cap layer over the p-type III-N layer. The III-N cap layer can cause an increase in the charge density of the 2DEG channel directly below the cap layer, and the p-type III-N layer can serve to prevent a parasitic 2DEG from forming in the III-N cap layer.

A semiconductor structure includes: a channel layer; an active layer over the channel layer, wherein the active layer is configured to form a two-dimensional electron gas (2DEG) to be formed in the channel layer along an interface between the channel layer and the active layer; a gate electrode over a top surface of the active layer; and a source/drain electrode over the top surface of the active layer; wherein the active layer includes a first layer and a second layer sequentially disposed therein from the top surface to a bottom surface of the active layer, and the first layer possesses a higher aluminum (Al) atom concentration compared to the second layer. An HEMT structure and an associated method are also disclosed.

Vertical integration schemes and circuit elements architectures for area scaling of semiconductor devices are described. In an example, an inverter structure includes a semiconductor fin separated vertically into an upper region and a lower region. A first plurality of gate structures is included for controlling the upper region of the semiconductor fin. A second plurality of gate structures is included for controlling the lower region of the semiconductor fin. The second plurality of gate structures has a conductivity type opposite the conductivity type of the first plurality of gate structures.

Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack including a quantum well layer; a plurality of gates disposed above the quantum well stack, wherein at least two of the gates are spaced apart in a first dimension above the quantum well stack, at least two of the gates are spaced apart in a second dimension above the quantum well stack, and the first and second dimensions are perpendicular; and an insulating material disposed above the quantum well stack, wherein the insulating material extends between at least two of the gates spaced apart in the first dimension, and the insulating material extends between at least two of the gates spaced apart in the second dimension.

Vertical integration schemes and circuit elements architectures for area scaling of semiconductor devices are described. In an example, an inverter structure includes a semiconductor fin separated vertically into an upper region and a lower region. A first plurality of gate structures is included for controlling the upper region of the semiconductor fin. A second plurality of gate structures is included for controlling the lower region of the semiconductor fin. The second plurality of gate structures has a conductivity type opposite the conductivity type of the first plurality of gate structures.

A novel image processing method is provided. In a display device in which a video signal is individually supplied to a screen divided into two, the entire screen is subjected to up-conversion processing after being divided, and another up-conversion processing is performed for a boundary portion of the screen divided into two. The divided up-conversion processing for the entire screen and the up-conversion processing for the boundary portion are performed in parallel with the use of a plurality of arithmetic units. The divided up-conversion processing for the entire screen and the up-conversion processing for the boundary portion can be performed using different algorithms.

Systems and methods are described herein to include an epitaxial metal layer between a rare earth oxide and a semiconductor layer. Systems and methods are described to grow a layered structure, comprising a substrate, a first rare earth oxide layer epitaxially grown over the substrate, a first metal layer epitaxially grown over the rare earth oxide layer, and a first semiconductor layer epitaxially grown over the first metal layer. Specifically, the substrate may include a porous portion, which is usually aligned with the metal layer, with or without a rare earth oxide layer in between.