Apparatus and circuits including transistors with different threshold voltages and methods of fabricating the same are disclosed. In one example, a semiconductor structure is disclosed. The semiconductor structure includes: a substrate; an active layer that is formed over the substrate and comprises a plurality of active portions; a polarization modulation layer comprising a plurality of polarization modulation portions each of which is disposed on a corresponding one of the plurality of active portions; and a plurality of transistors each of which comprises a source region, a drain region, and a gate structure formed on a corresponding one of the plurality of polarization modulation portions. The transistors have at least three different threshold voltages.

Disclosed herein are IC structures, packages, and devices that include III-N transistors integrated on the same support structure as non-III-N transistors (e.g., Si-based transistors), using semiconductor regrowth. In one aspect, a non-III-N transistor may be integrated with an III-N transistor by depositing a III-N material, forming an opening in the III-N material, and epitaxially growing within the opening a semiconductor material other than the III-N material. Since the III-N material may serve as a foundation for forming III-N transistors, while the non-III-N material may serve as a foundation for forming non-III-N transistors, such an approach advantageously enables implementation of both types of transistors on a single support structure. Proposed integration may reduce costs and improve performance by enabling integrated digital logic solutions for III-N transistors and by reducing losses incurred when power is routed off chip in a multi-chip package.

A method of manufacture and structure for a monolithic single chip single crystal device. The method can include forming a first single crystal epitaxial layer overlying the substrate and forming one or more second single crystal epitaxial layers overlying the first single crystal epitaxial layer. The first single crystal epitaxial layer and the one or more second single crystal epitaxial layers can be processed to form one or more active or passive device components. Through this process, the resulting device includes a monolithic epitaxial stack integrating multiple circuit functions.

A semiconductor thin film structure may include a substrate, a buffer layer on the substrate, and a semiconductor layer on the buffer layer, such that the buffer layer is between the semiconductor layer and the substrate. The buffer layer may include a plurality of unit layers. Each unit layer of the plurality of unit layers may include a first layer having first bandgap energy and a first thickness, a second layer having second bandgap energy and a second thickness, and a third layer having third bandgap energy and a third thickness. One layer having a lowest bandgap energy of the first, second, and third layers of the unit layer may be between another two layers of the first, second, and third layers of the unit layer.

A semiconductor body having a base carrier portion and a type III-nitride semiconductor portion is provided. The type III-nitride semiconductor portion includes a heterojunction and two-dimensional charge carrier gas. One or more ohmic contacts are formed in the type III-nitride semiconductor portion, the ohmic contacts forming an ohmic connection with the two-dimensional charge carrier gas. A gate structure is configured to control a conductive state of the two-dimensional charge carrier gas. Forming the one or more ohmic contacts comprises forming a structured laser-reflective mask on the upper surface of the type III-nitride semiconductor portion, implanting dopant atoms into the upper surface of the type III-nitride semiconductor portion, and performing a laser thermal anneal that activates the implanted dopant atoms.

An electronic component may include a carrier, and a thermoelectric sensor and a power transistor which are arranged on the carrier. The power transistor may include a base layer containing a transistor material chosen from among gallium nitride, aluminium gallium nitride, gallium arsenide, indium gallium, indium gallium nitride, aluminium nitride, indium aluminium nitride, and mixtures thereof. The electronic component may be configured so that the thermoelectric sensor generates an electric current under the effect of heating from the power transistor.

Provided is an electronic device using an interface between BaSnO.sub.3 and LaInO.sub.3, the electronic device including: a substrate formed of a metal oxide of non-SrTiO.sub.3 material a first buffer layer disposed on the substrate and formed of a BaSnO.sub.3 material; a BLSO layer disposed on at least a portion of the first buffer layer and formed of a (Ba.sub.1-x, La.sub.x)SnO.sub.3 material, wherein x has a value equal to or greater than 0 and less than or equal to 1; an LIO layer at least partially disposed on at least a portion of the BLSO layer so as to form an interface between the LIO layer and the BLSO layer, and formed of an LaInO.sub.3 material; and a first electrode layer at least partially in contact with the interface between the BLSO layer and the LIO layer, and formed of at least two or more separated portions.

A method for growing a semiconductor material over a Si-based substrate includes providing the Si-based substrate; growing a monocrystalline refractory-metal ceramic film directly over the Si-based substrate; and depositing a semiconductor film directly over the monocrystalline refractory-metal ceramic film. The monocrystalline refractory-metal ceramic film has a thickness less than 300 nm.

A method for manufacturing nitride semiconductor device includes a second step of forming, on a gate layer material film, a gate electrode film that is a material film of a gate electrode, a third step of selectively etching the gate electrode film to form the gate electrode 22 of a ridge shape, and a fourth step of selectively etching the gate layer material film to form a semiconductor gate layer 21 of a ridge shape with the gate electrode 22 disposed at a width intermediate portion of a front surface thereof. The third step includes a first etching step for forming a first portion 22A from an upper end to a thickness direction intermediate portion of the gate electrode 22 and a second etching step being a step differing in etching condition from the first etching step and being for forming a remaining second portion 22B of the gate electrode.

A nitride semiconductor device includes a first nitride semiconductor layer, a second nitride semiconductor layer formed on the first nitride semiconductor layer, a third nitride semiconductor layer that is disposed on the second nitride semiconductor layer, has a ridge portion at least at a portion thereof, and contains an acceptor type impurity, a gate electrode that is disposed on the ridge portion, and a source electrode and a drain electrode that, on the second nitride semiconductor layer, are disposed across the ridge portion from each other, and has an active region and a nonactive region. The nonactive region has a first region and a film thickness of the second nitride semiconductor layer in the first region differs from a film thickness of the second nitride semiconductor layer in a region of the active region in which the ridge portion, the source electrode, and the drain electrode are not formed.