A silicon carbide semiconductor device has a silicon carbide substrate and an insulating film. The silicon carbide substrate includes a termination region having a peripheral edge, and an element region surrounded by the termination region. The insulating film is provided on the termination region. The termination region includes a first impurity region having a first conductivity type, and a field stop region having the first conductivity type, being in contact with the first impurity region and having a higher impurity concentration than the first impurity region. The field stop region is at least partially exposed at the peripheral edge.

A semiconductor device includes a source/drain diffusion area, a first doped region and a gate. The source/drain diffusion area, defined between a first isolation structure and a second isolation structure, includes a source region, a drain region and a device channel. The first doped region, disposed along a first junction between the device channel and the first isolation structure, is separated from at least one of the source region and the drain region. The first doped region has a dopant concentration higher than that of the device channel. The gate is disposed over the source/drain diffusion area. The first doped region is located within a projected area of the gate onto the source/drain diffusion area, the first isolation structure and the second isolation structure. A length of the first doped region is shorter than a length of the gate in a direction from the source region to the drain region.

According to one embodiment, a semiconductor protection circuit includes a first MOS transistor that has a drain that is connected to an input terminal, a source that is connected to an output terminal, and a gate that is connected to a control terminal, a second MOS transistor that has a drain that is connected to the gate of the first MOS transistor and a source that is connected to the source of the first MOS transistor, a rectifier element that is connected in a forward direction from a gate of the second MOS transistor to the gate of the first MOS transistor, and a low-pass filter that is connected between the gate and the source of the second MOS transistor.

A power semiconductor device has a semiconductor body configured to conduct a load current in parallel to an extension direction between first and second load terminals of the power semiconductor device. The semiconductor body includes a doped contact region electrically connected to the second load terminal, a doped drift region having a dopant concentration that is smaller than a dopant concentration of the contact region, and an epitaxially grown doped transition region separated from the second load terminal by the contact region and that couples the contact region to the drift region. An upper subregion of the transition region is in contact with the drift region, and a lower subregion of the transition region is in contact with the contact region. The transition region has a dopant concentration of at least 0.5*10.sup.15 cm.sup.−3 for at least 5% of the total extension of the transition region in the extension direction.

A semiconductor device and a method for manufacturing the same are disclosed. The method comprises forming active patterns on a substrate that includes first and second logic cell regions adjacent to each other in a first direction, and forming on the substrate a device isolation layer exposing upper portions of the active patterns. The forming the active patterns comprises forming first line mask patterns extending parallel to each other in the first direction and running across the first and second logic cell regions, forming on the first line mask patterns an upper separation mask pattern including a first opening overlapping at least two of the first line mask patterns, forming first hardmask patterns from the at least two first line mask patterns, and etching the substrate to form trenches defining the active patterns.

A transistor cell includes, in a semiconductor body, a drift region of a first doping type, a source region of the first doping type, a body region of a second doping type, and a drain region of the first doping type. The body region is arranged between the source and drift regions. The drift region is arranged between the body and drain regions. A gate electrode is adjacent the body region and dielectrically insulated from the body region by a gate dielectric, and a field electrode is dielectrically insulated from the drift region by a field electrode dielectric. The drift region includes an avalanche region having a higher doping concentration than sections of the drift region adjacent the avalanche region and which is spaced apart from the field electrode dielectric in a direction perpendicular to the current flow direction. The field electrode is arranged in a needle-shaped trench.

A parameter is compared to a lower threshold. The parameter is a gate-to-source voltage that is associated with a first transistor or a drain current that is associated with the first transistor. The first transistor is a field effect transistor, and the first transistor is a power device. If one or more of at least one supplemental transistor is coupled to the first transistor, and the parameter is less than the lower threshold, a plurality of switches is controlled to decouple at least one of the at least one supplemental transistor from the first transistor.

A semiconductor arrangement is presented. The semiconductor arrangement comprises a semiconductor body, the semiconductor body including a semiconductor drift region, wherein the semiconductor drift region has dopants of a first conductivity type; a first semiconductor sense region and a second semiconductor sense region, wherein each of the first semiconductor sense region and the second semiconductor sense region is electrically connected to the semiconductor drift region and has dopants of a second conductivity type different from said first conductivity type; a first metal contact comprising a first metal material, the first metal contact being in contact with the first semiconductor sense region, wherein a transition between the first metal contact and the first semiconductor sense region forms a first metal-to-semiconductor transition; a second metal contact comprising a second metal material different from said first metal material, the second metal contact being separated from the first metal contact and in contact with the second semiconductor sense region, a transition between the second metal contact and the second semiconductor sense region forming a second metal-to-semiconductor transition different from said first metal-to-semiconductor transition; first electrical transmission means, the first electrical transmission means being arranged and configured for providing a first sense signal derived from an electrical parameter of the first metal contact to a first signal input of a sense signal processing unit; and second electrical transmission means separated from said first electrical transmission means, the second electrical transmission means being arranged and configured for providing a second sense signal derived from an electrical parameter of the second metal contact to a second signal input of said sense signal processing unit.

Disclosed is a power device, such as power MOSFET, and method for fabricating same. The device includes an upper trench situated over a lower trench, where the upper trench is wider than the lower trench. The device further includes a trench dielectric inside the lower trench and on sidewalls of the upper trench. The device also includes an electrode situated within the trench dielectric. The trench dielectric of the device has a bottom thickness that is greater than a sidewall thickness.

A semiconductor device includes a power transistor in a semiconductor substrate portion, where the semiconductor substrate portion includes a central portion and a kerf, components of the power transistor are arranged in the central portion, and the central portion has a thickness d. The semiconductor device also includes a support element disposed over a main surface of the central portion, where the support element has a smallest lateral extension t at a side adjacent to the main surface of the semiconductor substrate portion and a height h, where 0.1×h≦d≦4×h and 0.1×h≦t≦1.5×h.