The present invention provides semiconductor devices with super junction drift regions that are capable of blocking voltage. A super junction drift region is an epitaxial semiconductor layer located between a top electrode and a bottom electrode of the semiconductor device. The super junction drift region includes a plurality of pillars having P type conductivity, formed in the super junction drift region, which are surrounded by an N type material of the super junction drift region.

The application relates to a semiconductor switch element, including: a first vertical transistor device formed in a substrate and having a source region formed on a first side of the substrate and a drain region formed on a second side of the substrate vertically opposite to the first side; a second vertical transistor device formed laterally aside the first vertical transistor device in the same substrate and having a source region formed on the first side of the substrate and a drain region formed on the second side of the substrate; a conductive element arranged on the second side of the substrate and electrically connecting the drain regions of the vertical transistor devices; and a trench extending vertically into the substrate at the second side of the substrate, wherein at least a part of the conductive element is arranged in the trench.

There is disclosed the integration of a Schottky diode with a MOSFET, more in detail there is a free-wheeling Schottky diode and a power MOSFET on top of a buried grid material structure. Advantages of the specific design allow the whole surface area to be used for MOSFET and Schottky diode structures, the shared drift layer is not limited by Schottky diode or MOSFET design rules and therefore, one can decrease the thickness and increase the doping concentration of the drift layer closer to a punch through design compared to the state of the art. This results in higher conductivity and lower on-resistance of the device with no influence on the voltage blocking performance. The integrated device can operate at higher frequency. The risk for bipolar degradation is avoided.

A transistor device includes a semiconductor substrate having a first major surface, a cell field including transistor cells, and an edge termination region laterally surrounding the cell field. Each transistor cell includes a drift region of a first conductivity type, a first body region of a second conductivity type on the drift region, a source region of the first conductivity type on the first body region and a gate electrode. The transistor device further includes an elongate source contact having opposing first and second distal ends, the elongate source contact being in contact with the source region, and a second body region of the second conductivity type positioned in the semiconductor substrate. The second body region has a lateral extent such that it is spaced part from the second distal end of the elongate source contact and extends laterally beyond the first distal end of the elongate source contact.

A trench-gate MOSFET with electric field shielding region, has a substrate; a source electrode; a drain electrode; a semiconductor region with a first doping type formed on the substrate; a trench-gate, a plurality of electric field shielding regions with a second doping type formed under a surface of the semiconductor region, wherein the electric field shielding region intersects the trench-gate at an angle; a source electrode region formed on both sides of the trench-gate is divided into a plurality of source electrode sub-regions by the plurality of electric field shielding regions.

A semiconductor device includes a semiconductor body having an active area with active transistor cells. Each active transistor cell includes a columnar trench having a field plate and a mesa. An edge termination region that laterally surrounds the active area includes a transition region, an outer termination region, and inactive cells arranged in the transition region and outer termination region. Each inactive cell includes a columnar termination trench having a field plate and a termination mesa including a drift region. In the transition region, the termination mesa includes a body region arranged on the drift region and in the outer termination region the drift region of the termination mesa extends to the first surface. The edge termination region further includes a continuous trench positioned in the outer termination region, that laterally surrounds the columnar termination trenches, and is filled with at least one dielectric material.

A semiconductor device includes a junction field effect transistor (JFET) including a source electrode, a drain electrode, and a gate electrode, and a metal oxide semiconductor field effect transistor (MOSFET) including a source electrode, a drain electrode, and a gate electrode. The JFET and the MOSFET are cascode-connected such that the source electrode of the JFET and the drain electrode of the MOSFET are electrically connected. A gate voltage dependency of the JFET or a capacitance ratio of a mirror capacitance of the MOSFET to an input capacitance of the MOSFET is adjusted in a predetermined range.

A semiconductor device includes a MOSFET including a drift layer, a channel layer, a trench gate structure, a source layer, a drain layer, a source electrode, and a drain electrode. The trench gate structure includes a trench penetrating the channel layer and protruding into the drift layer, a gate insulating film disposed on a wall surface of the trench, and a gate electrode disposed on the gate insulating film. A portion of the trench protruding into the drift layer is entirely covered with a well layer, and the well layer is connected to the channel layer.

A field effect transistor includes a semiconductor substrate and multiple trenches disposed at a top surface of the semiconductor substrate. The trenches extend in a first direction at the top surface of the semiconductor substrate, and are disposed to be spaced apart in a direction perpendicular to the first direction. Connection regions are disposed below body regions. The connection regions extend in a second direction intersecting the first direction in a top view of the semiconductor substrate, and are spaced apart in a direction perpendicular to the second direction. Field relaxation regions are disposed below the connection regions and the trenches. The field relaxation regions extend in a third direction intersecting the first direction and the second direction in the top view of the semiconductor substrate, and are spaced apart in a direction perpendicular to the third direction.

Provided is a semiconductor device manufacturing method comprising: forming an impurity region including a first impurity on a semiconductor wafer; annealing the semiconductor wafer in a state where a lower surface of the semiconductor wafer is supported; and removing at least a part of the impurity region by removing a region including the lower surface of the semiconductor wafer. The first impurity may be oxygen. After the annealing, a maximum value of a concentration of the first impurity in the impurity region may be equal to or greater than 1×10.sup.18/cm.sup.3.